SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 59

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

Particular Pipeline Effects
Since up to four different instructions are processed simultaneously, additional hardware
has been spent in the C161U to consider all causal dependencies which may exist on
instructions in different pipeline stages without a loss of performance. This extra
hardware (ie. for 'forwarding' operand read and write values) resolves most of the
possible conflicts (eg. multiple usage of buses) in a time optimized way and thus avoids
that the pipeline becomes noticeable for the user in most cases. However, there are
some very rare cases, where the circumstance that the C161U is a pipelined machine
requires attention by the programmer. In these cases the delays caused by pipeline
conflicts can be used for other instructions in order to optimize performance.
An instruction, which calculates a physical GPR operand address via the CP register, is
mostly not capable of using a new CP value, which is to be updated by an immediately
preceding instruction. Thus, to make sure that the new CP value is used, at least one
instruction must be inserted between a CP-changing and a subsequent GPR-using
instruction, as shown in the following example:
I
I
I
An instruction, which calculates a physical operand address via a particular DPPn (n=0
to 3) register, is mostly not capable of using a new DPPn register value, which is to be
updated by an immediately preceding instruction. Thus, to make sure that the new DPPn
register value is used, at least one instruction must be inserted between a DPPn-
changing instruction and a subsequent instruction which implicitly uses DPPn via a long
or indirect addressing mode, as shown in the following example:
I
I
I
None of the RET, RETI, RETS, RETP or POP instructions is capable of correctly using
a new SP register value, which is to be updated by an immediately preceding instruction.
Thus, in order to use the new SP register value without erroneously performed stack
accesses, at least one instruction must be inserted between an explicitly SP-writing and
any subsequent of the just mentioned implicitly SP-using instructions, as shown in the
following example:
Data Sheet
n
n+1
n+2
n
n+1
n+2
Context Pointer Updating
Data Page Pointer Updating
Explicit Stack Pointer Updating
: SCXT CP, #0FC00h
: ....
: MOV R0, #dataX
: MOV DPP0, #4
: ....
: MOV DPP0:0000H, R1
; select a new context
; move contents of R1 to address location 01’0000
; must not be an instruction using a GPR
; write to GPR 0 in the new context
; select data page 4 via DPP0
; must not be an instruction using DPP0
; (in data page 4) supposed segmentation is enabled
59
Central Processor Unit
2001-04-19
C161U
H