SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 193

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

Early WR deactivation is controlled via the EWENx bits in the BUSCON registers (see
page 196). The WR signal will be shortened if bit EWENx is set to ’1’ signal. Default after
reset is a standard WR signal (EWENx = ’0’).
10.3
For situations, where the programmable waitstates are not enough, or where the
response (access) time of a peripheral is not constant, the C161U provides external bus
cycles that are terminated via a READY input signal (synchronous or asynchronous). In
this case the C161U first inserts a programmable number of waitstates (0...7) and then
monitors the READY line to determine the actual end of the current bus cycle. The
external device drives READY low in order to indicate that data have been latched (write
cycle) or are available (read cycle).
Figure 52
The READY function is enabled via the RDYENx bits in the BUSCON registers. When
this function is selected (RDYENx = ‘1’), only the lower 3 bits of the respective MCTC bit
field define the number of inserted waitstates (0...7), while the MSB of bit field MCTC
selects the READY operation:
MCTC.3 = ‘0’: Synchronous READY, ie. the READY signal must meet setup and hold
times.
MCTC.3 = ‘1’: Asynchronous READY, ie. the READY signal is synchronized internally.
Data Sheet
SREADY
AREADY
RD/WR
ALE
:
Evaluation (sampling) of the READY input
READY Controlled Bus Cycles
READY Controlled Bus Cycles
with active READY
Bus Cycle
1. WS
2. WS
193
1. WS 2. WS
extended via READY
Bus Cycle
External Bus Interface
2001-04-19
MCD02237
C161U