SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 279

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

C161U
Asynchronous/Synchr. Serial Interface
The baudrate generator is clocked with a clock (f
) which is derived via a prescaler from
DIV
the ASC input clock f
, e.g. 36 MHz. The baudrate timer is counting downwards and
MOD
can be started or stopped through the baudrate generator run bit CON_R. Each
underflow of the timer provides one clock pulse to the serial channel. The timer is
reloaded with the value stored in its 13-bit reload register each time it underflows. The
resulting clock f
is again divided by a factor for the baudrate clock (± 16 in
BRT
asynchronous modes and ± 4 in synchronous mode). The prescaler is selected by the
bits CON_BRS and CON_FDE. In the asynchronous operating modes, additionally to
the two fixed dividers a fractional divider prescaler unit is available which allows to select
prescaler divider ratios of n/512 with n=0-511. Therefore, the baudrate of ASC is
determined by the module clock, the content of S0FDV, the reload value of S0BG and
the operating mode (asynchronous or synchronous).
Register S0BG is the dual-function Baudrate Generator/Reload register. Reading BG
returns the content of the timer BR_VALUE (bits 15...13 return zero), while writing to
S0BG always updates the reload register (bits 15...13 are insiginificant).
An auto-reload of the timer with the content of the reload register is performed each time
CON_BG is written to. However, if CON_R=’0’ at the time the write operation to BG is
performed, the timer will not be reloaded until the first instruction cycle after CON_R=’1’.
For a clean baudrate initialization S0BG should only be written if CON_R=’0’. If S0BG is
written with CON_R=’1’, an unpredicted behaviour of the ASC may occur during running
transmit or receive operations.
12.1.7.1 Baudrates in Asynchronous Mode
For asynchronous operation, the baudrate generator provides a clock f
with 16 times
BRT
the rate of the established baudrate. Every received bit is sampled at the 7th, 8th and 9th
cycle of this clock. The clock divider circuitry, which generates the input clock for the 13-
bit baudrate timer, is extended by a fracxtional divider circuitry, which allows the
adjustment of more accurate baudrates and the extension of the baudrate range.
The baudrate of the baudrate generator depends on the following input clock, bits and
register values :
Input clock f
MOD
Selection of the baudrate timer input clock f
by bits CON_FDE and CON_BRS
DIV
If bit CON_FDE=1 (fractional divider) : value of register CON_FDV
value of the 13-bit reload register S0BG
The output clock of the baudrate timer with the reload register is the sample clock in the
asynchronous modes of the ASC. For baudrate calculations, this baudrate clock f
is
BR
derived from the sample clock f
by a division by 16.
DIV
Data Sheet
279
2001-04-19