SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 38

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

Data Sheet
When PLL operation is selected the CPU clock is a selectable multiple of the oscillator
frequency, ie. the input frequency. The table above lists the possible selections.
The PLL constantly synchronizes to the external clock signal. Due to the fact that the
external frequency is 1/F’th of the PLL output frequency the output frequency may be
slightly higher or lower than the desired frequency. This jitter is irrelevant for longer time
periods. For short periods (1...4 CPU clock cycles) it remains below 4%.
When the PLL detects a missing input clock signal it generates an interrupt request. This
warning interrupt indicates that the PLL frequency is no more locked, ie. no more stable.
This occurs when the input clock is unstable and especially when the input clock fails
completely, eg. due to a broken crystal. In this case the synchronization mechanism will
reduce the PLL output frequency down to the PLL’s basic frequency (2...5 MHz). The
basic frequency is still generated and allows the CPU to execute emergency actions in
case of a loss of the external clock.
Prescaler Operation
When pins P0.15-13 (P0H.7-5) are equal ’001’ during reset the CPU clock is derived
from the internal oscillator (input clock signal) by a 2:1 prescaler (see Table 8).
The frequency of f
the duration of an individual TCL) is defined by the period of the input clock f
The timings listed in the ’AC Characteristics’ of the data sheet that refer to TCLs
therefore can be calculated using the period of f
Direct Drive
When pins P0.15-13 (P0H.7-5) equal ’011’ during reset the clock system is directly
driven from the internal oscillator with the input clock signal, ie. f
The maximum input clock frequency depends on the clock signal’s duty cycle, because
the minimum values for the clock phases (TCLs) must be respected.
Oscillator Watchdog
The C161U provides an Oscillator Watchdog (OWD) which monitors the clock signal
generated by the on-chip oscillator (either with a crystal or via external clock drive) in
prescaler or direct drive mode. For this operation the PLL provides a clock signal which
is used to supervise transitions on the oscillator clock. This PLL clock is independent
from the XTAL1 clock. When the expected oscillator clock transitions are missing the
OWD activates the PLL Unlock / OWD interrupt node and supplies the CPU with the PLL
clock signal. Under these circumstances the PLL will oscillate with its basic frequency.
The OWD’s interrupt output can be disabled by setting bit OSCENBL = '0' (default after
reset) in SYSCON register. In this case, no oscillator watchdog interrupt request is
generated and the CPU clock signal is derived from the oscillator clock in any case.
CPU
is half the frequency of f
38
XTAL
XTAL
and the high and low time of f
for any TCL.
Architectural Overview
OSC
= f
CPU
.
XTAL
2001-04-19
C161U
CPU
.
(ie.