SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 346

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

Data Sheet
might be read from the fifo; this interrupt is connected to the EPEC which in nomal
functionality does this transfer).
By default, the bits 8 and 15 of the CMD register (auto flush enable and tx_protect)
should be set.
15.7.1
After a system-reset, the USB-block expects the configurator of the UDC to be
transferred via the tx-fifo(0) like a normal in-transfer. Best is using the EPEC for this
endpoint. The source-pointer must be programmed to a memory-block containing the 85
bytes of the configurator, destination to usbd_txwr-register(0) and the length-register to
85 bytes. After starting the EPEC, it will transfer the configurator to the USB-block and
after having transferred all the data, the EPEC-interrupt is generated and if the
configurator went through the fifo, the udc_tx_done-interrupt(0) is also generated.
In order to allow generation of a next interrupt-pulse of the EPEC, SW must read the
EPEC-interrupt-register and clear the interrupt-bit of endpoint 0 by writing a ‘1’ to it.
15.7.2
An In-transfer means that the device will send data to the host by using endpointX. This
transfer is started by a bulk_in, interrupt, control_in or iso_in request from the host.
• SW sets up source-pointer (to a memory-block containing the data to be sent), a
• SW writes EPEC-start, EPEC transferres the data from the memory to the USB-fifoX;
• when EPEC has transferred all the data, it generates the EPEC-interrupt; SW must
• when the transfer over the USB is finished, the udc_tx_done-interruptX is generated
destination-pointer
maxpacketlength) of the EPEC for the endpoint on which the transfer is to be done;
the packetlength must always be the maxpacketlength for this endpoint for interrupt-,
bulk_in or control_in-transfers except for the last packet to be transferred, for
isochronous_in-endpoints this endpoint must be according to the sequence of
packetlengths and the data which is available to be sent.
If SW wants to send a packet of zero bytes, it must not use the EPEC, but must write
‘1’ to the corresponding usbd_tx_eod-register of the USB
when host requests for the data, it is transferred through the fifo to the host; each time,
the USB-block has space in the fifo and may accept a write into the usbd_txwr-
register, the udc_txwr-interrupt is generated (for normal functionality this can be
ignored as the EPEC uses this as a handshake for the next transfer)
read the EPEC-interrupt-register and clear the (to the endpoint) corresponding bit by
writing a ‘1’ to it
and SW can check the corresponding bit in the Status-Register, wheather the transfer
was successful or not; this is for bulk, interrupt and control-Endpoints only, not for
Isochonous Endpoints (where no ACK will be sent as Handshake)
Writing the configuration-value
In-Transfer (Transmit)
(usbd_txwr-registerX)
346
and
the
USB Interface Controller
packetlenght
2001-04-19
C161U
(usually