SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 124

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

Data Sheet
is a branch instruction (without cache hit), or if it reads an operand from internal code
memory, or if it is executed out of the internal RAM.
Note: A bus access in this context includes all delays which can occur during an external
7.7
PEC response time defines the time from an interrupt request flag of an enabled interrupt
source being set until the PEC data transfer being started. The basic PEC response time
for the C161U is 2 instruction cycles.
Figure 25
In Figure 25 the respective interrupt request flag is set in cycle 1 (fetching of instruction
N). The indicated source wins the prioritization round (during cycle 2). In cycle 3 a PEC
transfer “instruction” is injected into the decode stage of the pipeline, suspending
instruction N+1 and clearing the source's interrupt request flag to '0'. Cycle 4 completes
the injected PEC transfer and resumes the execution of instruction N+1.
All instructions that entered the pipeline after setting of the interrupt request flag (N+1,
N+2) will be executed after the PEC data transfer.
Note: When instruction N reads any of the PEC control registers PECC7...PECC0, while
The minimum PEC response time is 3 states (6 TCL). This requires program execution
from the internal code memory, no external operand read requests and setting the
interrupt request flag during the last state of an instruction cycle. When the interrupt
request flag is set during the first state of an instruction cycle, the minimum PEC
response time under these conditions is 4 state times (8 TCL).
Pipeline Stage Cycle 1
FETCH
DECODE
EXECUTE
WRITEBACK
IR-Flag
bus cycle.
a PEC request wins the current round of prioritization, this round is repeated and
the PEC data transfer is started one cycle later.
PEC Response Times
Pipeline Diagram for PEC Response Time
1
0
N
N - 1
N - 2
N - 3
PEC Response Time
Cycle 2
N + 1
N
N - 1
N - 2
124
Cycle 3
N + 2
PEC
N
N - 1
Interrupt and Trap Functions
Cycle 4
N + 2
PEC
N
N + 1
2001-04-19
C161U