SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 240

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SAF-C161U-LF V1.3

Manufacturer Part Number
SAF-C161U-LF V1.3
Description
IC MCU ISDN 16BIT TTL TQFP-100
Manufacturer
Infineon Technologies
Series
C16xxr
Datasheet

Specifications of SAF-C161U-LF V1.3

Core Processor
C166
Core Size
16-Bit
Speed
36MHz
Connectivity
EBI/EMI, SPI, UART/USART, USB
Peripherals
POR, PWM, WDT
Number Of I /o
56
Program Memory Type
ROMless
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Other names
SAFC161ULFV1.3X
SAFC161ULFV13XP
SP000007502
Data Sheet
GPT Clock Control Register
GPTCLC (FE4C
Function Control Registers
The operating mode of the core timer T3 is configured and controlled via its
bitaddressable control register T3CON.
T3CON
Timer 3 Control Register
IREN
Bit
GPTDISR
GPTDISS
SUSPEN
EXDISR
Field
T3I
15
15
T3
0
RDIR
14
T3
14
0
T3CH
DIR
13
13
0
Bits
[2:0]
H
Function
GPT Disable Request Bit
GPTDISR = ‘0’:
GPTDISR = ‘1’:
GPT Disable Status Bit
GPTDISS = ‘0’:
GPTDISS = ‘1’:
Peripheral Suspend Enable Bit for OCDS
SUSPEN = ‘0’:
SUSPEN = ‘1’:
External Disable Request
EXRDIS = ‘0’:
EXRDIS = ‘1’:
)
EDG
12
T3
12
0
E
Type Value
rw
FM1
11
11
0
OTL
10
T3
0
10
T3OE
GPT clock disable not requested
GPT clock disable requested
GPT clock enabled
GPT clock disabled
Peripheral suspend disabled
Peripheral suspend enabled
External clock disable Request is enabled
External clock disable Request is disabled
9
0
Reset Value: 0000
Reset Value: 0000
9
Description
Timer 3 Input Parameter Selection
Timer mode see Table 44 for encoding
Gated Timer see Table 44 for encoding
Counter mode see Table 45 for encoding
Incremental Interface mode see Table 46 for
encoding
UDE
8
0
T3
8
240
T3UD T3R
7
0
7
6
0
6
H
H
5
0
5
General Purpose Timer Unit
T3M
4
0
4
DISR
EX
rw
3
3
SUS
PEN
rw
2
2
DISS
GPT
2001-04-19
1
r
T3I
1
C161U
DISR
GPT
rw
0
0

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