SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 78

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SAF-C161U-LF V1.3

Manufacturer Part Number
SAF-C161U-LF V1.3
Description
IC MCU ISDN 16BIT TTL TQFP-100
Manufacturer
Infineon Technologies
Series
C16xxr
Datasheet

Specifications of SAF-C161U-LF V1.3

Core Processor
C166
Core Size
16-Bit
Speed
36MHz
Connectivity
EBI/EMI, SPI, UART/USART, USB
Peripherals
POR, PWM, WDT
Number Of I /o
56
Program Memory Type
ROMless
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Other names
SAFC161ULFV1.3X
SAFC161ULFV13XP
SP000007502
Data Sheet
Figure 18
Several addressing modes use register CP implicitly for address calculations. The
addressing modes mentioned below are described in chapter “Instruction Set
Summary”.
Short 4-Bit GPR Addresses (mnemonic: Rw or Rb) specify an address relative to the
memory location specified by the contents of the CP register, ie. the base of the current
register bank.
Depending on whether a relative word (Rw) or byte (Rb) GPR address is specified, the
short 4-bit GPR address is either multiplied by two or not before it is added to the content
of register CP (see figure below). Thus, both byte and word GPR accesses are possible
in this way.
GPRs used as indirect address pointers are always accessed wordwise. For some
instructions only the first four GPRs can be used as indirect address pointers. These
GPRs are specified via short 2-bit GPR addresses. The respective physical address
calculation is identical to that for the short 4-bit GPR addresses.
Register Bank Selection via Register CP
Context
Pointer
78
Internal RAM
R15
R14
R13
R12
R10
R11
R9
R8
R7
R6
R5
R4
R3
R2
R0
R1
Central Processor Unit
(CP) + 30
(CP) + 28
(CP) + 2
(CP)
MCD02003
.
.
.
2001-04-19
C161U

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