SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 37

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

Note: All supported clock modes for the C161U are shown in Table 8. Because of the
Table 8
PLL Operation
On power-up the PLL provides a stable clock signal within ca. 1 ms after VDD has
reached 3.3 V 10%, even if there is no external clock signal (in this case the PLL will run
on its basic frequency of 2...5 MHz). The PLL starts synchronizing with the external clock
signal as soon as it is available. Within ca. 1 ms after stable oscillations of the external
clock within the specified frequency range the PLL will be synchronous with this clock at
a frequency of F * f
Note: If the C161U is required to operate on the desired CPU clock directly after reset
Data Sheet
P0H.7-P0H.5 Frequency
0
0
0
1
1
1
1
0
1
1
0
1
1
0
0
1
1
0
1
1
limited size of the register, there are not all combinations adjustable, which can be
derived theoretical from .
make sure that RSTIN remains active until the PLL has locked (ca. 1 ms).
1
0
1
0
1
0
1
0
0
1
C161U Clock Generation Modes
f
f
XTAL
XTAL
f
f
f
f
f
f
f
XTAL
XTAL
XTAL
XTAL
XTAL
XTAL
XTAL
f
XTAL
USB Interface is used (USB clock must be 48 MHz)
OSC
* 1.125
* 0.375
* 0.5
* 1.5
* 1.0
* 6.0
* 3.0
* 4.5
* 4.5
* 3
, ie. the PLL locks to the external clock.
direct drive, D1 not active, D2 active, PLL free running (2..5 MHz)
Note: The PLL can be switched off completely by setting bit
D1 not active, D2 not active, F = 1.5
direct drive, D1 not active, D2 not active, PLL free running (2..5
MHz)
Note: The PLL can be switched off completely by setting bit
D1 not active, D2 not active, F = 6.0
D1 active, D2 active, F = 1.125
D1 not active, D2 not active, F = 3.0
D1 not active, D2 not active, F = 4.5, Default Mode
D1 active, D2 active, F = 0.375
D1 not active, D2 not active, F = 3.0
f
D1 not active, D2 not active, F = 4.5, Default Mode
f
USB
USB
USB Interface is NOT used
=
=
def
def
PLLDIS = ’1’ (SYSCON3.13, see page 393).
PLLDIS = ’1’ (SYSCON3.13, see page 393).
48 MHz
48 MHz
37
Τ
Τ
f
Divider Activation
f
XTAL
XTAL
= 8 MHz
= 8 MHz
Architectural Overview
Τ
Τ
f
CPU
f
CPU
= 24 MHz
= 36 MHz
2001-04-19
C161U