SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 110

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

Data Sheet
Normal Interrupt Processing and PEC Service
During each instruction cycle one out of all sources which require PEC or interrupt
processing is selected according to its interrupt priority. This priority of interrupts and
PEC requests is programmable in two levels. Each requesting source can be assigned
to a specific priority. A second level (called “group priority”) allows to specify an internal
order for simultaneous requests from a group of different sources on the same priority
level. At the end of each instruction cycle the one source request with the highest current
priority will be determined by the interrupt system. This request will then be serviced, if
its priority is higher than the current CPU priority in register PSW.
Interrupt System Register Description
Interrupt processing is controlled globally by register PSW through a general interrupt
enable bit (IEN) and the CPU priority field (ILVL). Additionally the different interrupt
sources are controlled individually by their specific interrupt control registers (...IC).
Thus, the acceptance of requests by the CPU is determined by both the individual
interrupt control registers and the PSW. PEC services are controlled by the respective
PECCx register and the source and destination pointers, which specify the task of the
respective PEC service channel.
Exception Condition
Class B Hardware Traps:
Reserved
Software Traps
TRAP Instruction
Undefined Opcode
Protected Instruction
Fault
Illegal Word Operand
Access
Illegal Instruction Access
Illegal External Bus
Access
Trap
Flag
UNDOPC
PRTFLT
#
ILLOPA
ILLINA
ILLBUS
110
Trap
Vector
BTRAP
BTRAP
BTRAP
BTRAP
BTRAP
Interrupt and Trap Functions
Vector
Location
00’0028
[2C
00’0028
00’0028
00’0028
00’0028
3C
Any
[00’0000
–
00’01FC
in steps
of 4
H
H
H
]
–
H
H
H
H
H
H
H
]
Trap
Number
0A
0A
0A
0A
0A
[0B
0F
Any
[00
7F
H
H
H
H
H
H
H
H
H
]
]
–
–
2001-04-19
C161U
Trap
Prio.
I
I
I
I
I
Curr
ent
CPU
Prio.