SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 206

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

Data Sheet
RP0H (F108
Note: RP0H cannot be changed via software, but rather allows to check the current
Precautions and Hints
• The external bus interface is enabled as long as at least one of the BUSCON registers
• PORT1 will output the intra-segment address as long as at least one of the BUSCON
• Not all address areas defined via registers ADDRSELx may overlap each other. The
• The address areas defined via registers ADDRSELx may overlap internal address
• For any access to an internal address area the EBC will remain inactive (see EBC Idle
Bit
WRC
CSSEL
SALSEL
CLKCFG
15
-
has its BUSACT bit set.
registers selects a demultiplexed external bus, even for multiplexed bus cycles.
operation of the EBC will be unpredictable in such a case. See chapter „Address
Window Arbitration“.
areas. Internal accesses will be executed in this case.
State).
configuration.
14
-
H
13
/ 84
-
Function
Write Configuration
0: Pins WR and BHE operate as WRL and WRH signals
1: Pins WR and BHE operate as WR and BHE signals
Chip Select Line Selection (Number of active CS outputs)
0 0: 3 CS lines: CS2...CS0
0 1: 2 CS lines: CS1...CS0
1 0: No CS lines at all
1 1: 4 CS lines: CS3...CS0 (Default without pulldowns)
Segment Address Line Selection (Number of active segment address
outputs)
0 0: 4-bit segment address: A19...A16
0 1: No segment address lines at all
1 0: 5-bit segment address: A20...A16
1 1: 2-bit segment address: A17...A16 (Default without pulldowns)
Clock Generation Mode Configuration
These pins define the clock generation mode, ie. the mechanism how the
the internal CPU clock is generated from the externally applied (XTAL1)
input clock.
H
)
12
-
11
-
10
-
9
-
8
-
SFR
206
7
CLKCFG
6
r
5
SALSEL
4
External Bus Interface
r
Reset Value: - - XX
3
2
CSSEL
r
2001-04-19
1
C161U
WRC
0
r
H