SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 57

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SAF-C161U-LF V1.3

Manufacturer Part Number
SAF-C161U-LF V1.3
Description
IC MCU ISDN 16BIT TTL TQFP-100
Manufacturer
Infineon Technologies
Series
C16xxr
Datasheet

Specifications of SAF-C161U-LF V1.3

Core Processor
C166
Core Size
16-Bit
Speed
36MHz
Connectivity
EBI/EMI, SPI, UART/USART, USB
Peripherals
POR, PWM, WDT
Number Of I /o
56
Program Memory Type
ROMless
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Other names
SAFC161ULFV1.3X
SAFC161ULFV13XP
SP000007502
Instruction pipelining increases the average instruction throughput considered over a
certain period of time. In the following, any execution time specification of an instruction
always refers to the average execution time due to pipelined parallel instruction
processing.
Figure 13
Standard Branch Instruction Processing
Instruction pipelining helps to speed sequential program processing. In the case that a
branch is taken, the instruction which has already been fetched providently is mostly not
the instruction which must be decoded next. Thus, at least one additional machine cycle
is normally required to fetch the branch target instruction. This extra machine cycle is
provided by means of an injected instruction (see Figure 14).
Figure 14
Data Sheet
WRITEBACK
WRITEBACK
EXECUTE
EXECUTE
DECODE
DECODE
FETCH
FETCH
time
time
Sequential Instruction Pipelining
Standard Branch Instruction Pipelining
BRANCH
1 Machine
1 Machine
Cycle
Cycle
. . .
. . .
I
I
n
1
BRANCH
I
. . .
n+2
I
I
I
2
1
n
BRANCH
(I
I
TARGET
INJECT
57
Injection
I
I
I
I
3
2
1
n
)
BRANCH
I
(I
TARGET+1
I
TARGET
INJECT
I
I
I
I
4
3
2
1
)
I
I
(I
TARGET+2
TARGET+1
Central Processor Unit
I
TARGET
INJECT
I
I
I
I
5
4
3
2
)
I
I
I
TARGET+3
TARGET+2
TARGET+1
I
TARGET
I
I
I
I
6
5
4
3
2001-04-19
C161U

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