SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 178

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SAF-C161U-LF V1.3

Manufacturer Part Number
SAF-C161U-LF V1.3
Description
IC MCU ISDN 16BIT TTL TQFP-100
Manufacturer
Infineon Technologies
Series
C16xxr
Datasheet

Specifications of SAF-C161U-LF V1.3

Core Processor
C166
Core Size
16-Bit
Speed
36MHz
Connectivity
EBI/EMI, SPI, UART/USART, USB
Peripherals
POR, PWM, WDT
Number Of I /o
56
Program Memory Type
ROMless
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Other names
SAFC161ULFV1.3X
SAFC161ULFV13XP
SP000007502
Data Sheet
Single Chip Mode
Single chip mode is entered, when pin EA is high during reset. In this case register
BUSCON0 is initialized with 0000
is enabled.
In single chip mode the C161U operates only with and out of internal resources. No
external bus is configured and no external peripherals and/or memory can be accessed.
Also no port lines are occupied for the bus interface. When running in single chip mode,
however, external access may be enabled by configuring an external bus under software
control.
Note: Any attempt to access a location in the external memory space in single chip mode
10.1
When the external bus interface is enabled (bit BUSACTx=’1’) and configured (bitfield
BTYP), the C161U uses a subset of its port lines together with some control lines to build
the external bus.
The bus configuration (BTYP) for the address windows (BUSCON4...BUSCON1) is
selected via software typically during the initialization of the system.
The bus configuration (BTYP) for the default address range (BUSCON0) is selected via
PORT0 during reset, provided that pin EA is low during reset. Otherwise BUSCON0 may
be programmed via software just like the other BUSCON registers.
The 16 MByte address space of the C161U is divided into 256 segments of 64 KByte
each. The 16-bit intra-segment address is output on PORT0 for multiplexed bus modes
or on PORT1 for demultiplexed bus modes. When segmentation is disabled, only one 64
KByte segment can be used and accessed. Otherwise additional address lines may be
output on Port 4, and/or several chip select lines may be used to select different memory
banks or peripherals. These functions are selected during reset via bitfields SALSEL and
CSSEL of register RP0H, respectively.
Note: Bit SGTDIS of register SYSCON defines, if the CSP register is saved during
BTYP
Encoding
0 0
0 1
1 0
1 1
results in the hardware trap ILLBUS.
interrupt entry (segmentation active) or not (segmentation disabled).
External Bus Modes
External Data Bus Width
8-bit Data
8-bit Data
16-bit Data
16-bit Data
H
, which also resets bit BUSACT0, so no external bus
178
External Address Bus Mode
Demultiplexed Addresses
Multiplexed Addresses
Demultiplexed Addresses
Multiplexed Addresses
External Bus Interface
2001-04-19
C161U

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