SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 39

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

C161U
Architectural Overview
Note: The CPU clock source is only switched back to the oscillator clock after a
hardware reset.
3.4
On-Chip Peripheral Blocks
C161U clearly separates peripherals from the core. This structure permits the maximum
number of operations to be performed in parallel and allows peripherals to be added or
deleted from family members without modifications to the core. Each functional block
processes data independently and communicates information over common buses.
Peripherals are controlled by data written to the respective Special Function Registers
(SFRs).
These
SFRs
are
located
either
within
the
standard
SFR
area
(00’FE00
...00’FFFF
) or within the extended ESFR area (00’F000
...00’F1FF
).
H
H
H
H
These built in peripherals either allow the CPU to interface with the external world, or
provide functions on-chip that otherwise were to be added externally in the respective
system.
C161U peripherals are:
• Two General Purpose Timer Blocks (GPT1 and GPT2)
• An Asynchronous/Synchronous Serial Interface (ASC)
• A High-Speed Synchronous Serial Interface (SSC)
• An Universal Serial Bus Interface (USB)
• A Watchdog Timer (WDT)
• Six I/O ports with a total of 56 I/O lines
Each peripheral also contains a set of Special Function Registers (SFRs), which control
the functionality of the peripheral and temporarily store intermediate data results. Each
peripheral has an associated set of status flags. Individually selected clock signals are
generated for each peripheral from binary multiples of the CPU clock.
Peripheral Interfaces
The on-chip peripherals generally have two different types of interfaces, an interface to
the CPU and an interface to external hardware. Communication between CPU and
peripherals is performed through Special Function Registers (SFRs) and interrupts. The
SFRs serve as control/status and data registers for the peripherals. Interrupt requests
are generated by the peripherals based on specific events which occur during their
operation (eg. operation complete, error, etc.).
For interfacing with external hardware, specific pins of the parallel ports are used, when
an input or output function has been selected for a peripheral. During this time, the port
pins are controlled by the peripheral (when used as outputs) or by the external hardware
which controls the peripheral (when used as inputs). This is called the 'alternate (input
or output) function' of a port pin, in contrast to its function as a general purpose I/O pin.
Data Sheet
39
2001-04-19