SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 347

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

• for non-Iso-transfers: if fhe transfer was ACK’d, the next packet can be set up for
• SW must set up again the EPEC source-, destination-pointer and packetlength and
If SW has already set up data in a tx-fifo and now, e.g. host changes the configuration
or interfaces, SW can use a write into the command-register to flush the fifo of the
corresponding endpoint. Before doing this, the EPEC-channel must be disabled or
reprorgammed, otherwise the next pending bytes will be transferred into the tx-fifo.
15.7.3
During an Out-transfer, host is transferring data to the device. SW must provide an free
memory-block for each endpoint and set up the EPEC for moving arriving data from the
USB-block to a free memory-location.
• SW provides an free memory-block and sets up source- (usbd_rxrr-registerX),
• when host sends data, it is forwarded through the fifo’s and with every transferred
• EPEC generates an EPEC-interrupt when it has transferred all the data into the
• when USB-block has finished the whole transfer, it generates the udc_rx_done-
• in order to prepare a receive on this endpoint again SW must provide a new free
15.7.4
Setup-packets are treated without the EPEC. If host sends a setup-packet which is
forwarded to the CPU (there are only three commands: get_descriptor, set_descriptor
and synch_frame all the other ones are treated internally), and the packet is valid, the
Data Sheet
transmission, otherwise, host expects the same data to be resent
start the transfer
destination-pointer (free memory-block) and packet lenght of the EPEC and sets the
TXR_ENAx bit (refer to Table 18, “EPEC_CTRL_REGx Source Pointer Register,” on
page 101); the packetlength supported by the EPEC must always be an even number
of bytes (in receive-direction the EPEC only does word-transfers) and have at least
space for the maxpacketlength of the endpoint.
word that can be read from usbd_rxrr-registerX the usbd_rxrr-interruptX is set (for
normal functionality this can be ignored); EPEC transferes this data into the memory
memory (this interrupt is generated shortly after the USB-block has generated the
udc_rx_done-interrupt); SW must read the EPEC-interrupt-register and clear the (to
the endpoint) corresponding bit in this register by writing a ‘1’ into it
interrupt; SW must then read the usbd_rx_bytecnt-register, in order to determine the
number of bytes of the received packet and to release the interlocking of the fifo for
the next transfer; the most significant bit in this register contains also the status-bit of
the status-register and shows whether this packet had transmission-errors or not
if host has sent a packet of zero lenght, no rxrr-interrupt is generated but only a
rx_done-interrupt; here also SW must read the rxbytecountX-register
memory-block, set up the source-, destination-pointer and packetlength of the EPEC
and write the start-bit
Out-Transfer (Receive)
Reading out Setup-Packets
347
USB Interface Controller
2001-04-19
C161U