SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 111

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

7.2
All interrupt control registers are organized identically. The lower 8 bits of an interrupt
control register contain the complete interrupt status information of the associated
source, which is required during one round of prioritization, the upper 8 bits of the
respective register are reserved. All interrupt control registers are bit-addressable and all
bits can be read or written via software. This allows each interrupt source to be
programmed or modified with just one instruction. When accessing interrupt control
registers through instructions which operate on word data types, their upper 8 bits
(15...8) will return zeros, when read, and will discard written data.
The layout of the Interrupt Control registers shown below applies to each xxIC register,
where xx stands for the mnemonic for the respective source.
xxIC (yyyy
Interrupt Request Flag is set by hardware whenever a service request from the
respective source occurs. It is cleared automatically upon entry into the interrupt service
routine or upon a PEC service. In the case of PEC service the Interrupt Request flag
remains set, if the COUNT field in register PECCx of the selected PEC channel
Data Sheet
Bit
GLVL
ILVL
xxIE
xxIR
15
-
14
-
H
Interrupt Control Registers
/ zz
13
-
H
Function
Group Level
Defines the internal order for simultaneous requests of the same priority.
3: Highest group priority
0: Lowest group priority
Interrupt Priority Level
Defines the priority level for the arbitration of requests.
F
0
Interrupt Enable Control Bit (individually enables/disables a specific
source)
‘0’: Interrupt request is disabled
‘1’: Interrupt Request is enabled
Interrupt Request Flag
‘0’: No request pending
‘1’: This source has raised an interrupt request
)
H
H
: Lowest priority level
: Highest priority level
12
-
11
-
10
-
9
-
<SFR area>
8
-
111
xxIR
rw
7
xxIE
rw
6
5
Interrupt and Trap Functions
4
ILVL
rw
Reset Value: - - 00
3
2
2001-04-19
1
GLVL
rw
C161U
0
H