SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 270

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

Data Sheet
12.1.5.1 Asynchronous Data Frames
8-Bit Data Frames
8-bit data frames either consist of 8 data bits D7...D0 (CON_M=’001
D6...D0 plus an automatically generated parity bit (CON_M=’011
or even, depending on bit CON_ODD. An even parity bit will be set, if the modulo-2-sum
of the 7 data bits is ‘1’. An odd parity bit will be cleared in this case. Parity checking is
enabled via bit CON_PEN (always OFF in 8-bit data mode). The parity error flag
CON_PE will be set along with the error interrupt request flag, if a wrong parity bit is
received. The parity bit itself will be stored in bit RBUF.7.
Figure 79
9-Bit Data Frames
9-bit data frames either consist of 9 data bits D8...D0 (CON_M=’100
D7...D0 plus an automatically generated parity bit (CON_M=’111
D7...D0 plus wake-up bit (CON_M=’101
CON_ODD. An even parity bit will be set, if the modulo-2-sum of the 8 data bits is ‘1’. An
odd parity bit will be cleared in this case. Parity checking is enabled via bit CON_PEN
(always OFF in 9-bit data and wake-up mode). The parity error flag CON_PE will be set
along with the error interrupt request flag, if a wrong parity bit is received. The parity bit
itself will be stored in bit RBUF.8.
CON_M=001
CON_M=011
Asynchronous 8-Bit Frames
B
B
Start
Start
Bit
Bit
0
0
D0
LSB
D0
LSB
D1
D1
D2
D2
B
’). Parity may be odd or even, depending on bit
7 Data Bits
270
10-/11-Bit UART Frame
D3
10-/11-Bit UART Frame
D3
8 Data Bits
Asynchronous/Synchr. Serial Interface
D4
D4
D5 D6
D5
D6
D7
Parit
B
’). Parity may be odd
B
B
’) or of 8 data bits
’), or of 7 data bits
Stop
B
(1st)
(1st)
Stop
Bit
Bit
’), of 8 data bits
1
1
(2nd)
Stop
(2nd)
Stop
Bit
Bit
1
2001-04-19
1
C161U