SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 273

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

12.1.5.3 Asynchronous Reception
Asynchronous reception is initiated by a falling edge (1-to-0 transition) on pin P3.11/
RXD, provided that bits CON_R and CON_REN are set. The receive data input pin
P3.11/RXD is sampled at 16 times the rate of the selected baudrate. A majority decision
of the 7th, 8th and 9th sample determines the effective bit value. This avoids erroneous
results that may be caused by noise.
If the detected value is not a '0' when the start bit is sampled, the receive circuit is reset
and waits for the next 1-to-0 transition at pin P3.11/RXD. If the start bit proves valid, the
receive circuit continues sampling and shifts the incoming data frame into the receive
shift register.
When the last stop bit has been received, the content of the receive shift register is
transferred to the receive data buffer register S0RBUF. Simultaneously, the receive
interrupt request line RIR is activated after the 9th sample in the last stop bit time slot (as
programmed), regardless whether valid stop bits have been received or not. The receive
circuit then waits for the next start bit (1-to-0 transition) at the receive data input pin.
The receiver input pin P3.11/RXD must be configured for input.
Asynchronous reception is stopped by clearing bit CON_REN. A currently received
frame is completed including the generation of the receive interrupt request and an error
interrupt request, if appropriate. Start bits that follow this frame will not be recognized.
Note: In wake-up mode received frames are only transferred to the receive buffer
12.1.5.4 IrDA Mode
The duration of the IrDA pulse is normally 3/16 of a bit period. The IrDA standard also
allows the pulse duration being independent of the baudrate or bit period. In this case
the transmitted pulse has always the width corresponding to the 3/16 pulse width at
115.2 kBaud which is 1.627 µs. Both, bit period dependend or fixed IrDA pulse width
generation can be selected. The IrDA pulse width mode is selected by bit PMW_IRPW.
In case of fixed IrDA pulse width generation, the lower 8 bits in register PMW are used
to adapt the IrDA pulse width to a fixed value of e.g. 1.627 µs. The fixed IrDA pulse width
is generated by a programmable timer as shown in Figure 82.
Data Sheet
register, if the 9th bit (the wake-up bit) is ‘1’. If this bit is ‘0’, no receive interrupt
request will be activated and no data will be transferred.
273
Asynchronous/Synchr. Serial Interface
2001-04-19
C161U