SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 58

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

Data Sheet
If a conditional branch is not taken, there is no deviation from the sequential program
flow, and thus no extra time is required. In this case the instruction after the branch
instruction will enter the decode stage of the pipeline at the beginning of the next
machine cycle after decode of the conditional branch instruction.
Cache Jump Instruction Processing
C161U incorporates a jump cache to optimize conditional jumps, which are processed
repeatedly within a loop. Whenever a jump on cache is taken, the extra time to fetch the
branch target instruction can be saved and thus the corresponding cache jump
instruction in most cases takes only one machine cycle.
This performance is achieved by the following mechanism:
Whenever a cache jump instruction passes through the decode stage of the pipeline for
the first time (and provided that the jump condition is met), the jump target instruction is
fetched as usual, causing a time delay of one machine cycle. In contrast to standard
branch instructions, however, the target instruction of a cache jump instruction (JMPA,
JMPR, JB, JBC, JNB, JNBS) is additionally stored in the cache after having been
fetched.
After each repeatedly following execution of the same cache jump instruction, the jump
target instruction is not fetched from progam memory but taken from the cache and
immediatly injected into the decode stage of the pipeline (see Figure 15).
A time saving jump on cache is always taken after the second and any further occurrence
of the same cache jump instruction, unless an instruction which, has the fundamental
capability of changing the CSP register contents (JMPS, CALLS, RETS, TRAP, RETI),
or any standard interrupt has been processed during the period of time between two
following occurrences of the same cache jump instruction.
Figure 15
WRITEBACK
EXECUTE
DECODE
FETCH
Cache Jump Instruction Pipelining
Cache Jmp
1 Machine
Cycle
I
. . .
n+2
I
n
1st loop iteration
Cache Jmp
(I
I
TARGET
INJECT
Injection
I
n
)
Cache Jmp
I
(I
TARGET+1
I
TARGET
INJECT
58
)
Cache Jmp
Repeated loop iteration
I
. . .
n+2
I
n
Central Processor Unit
Cache Jmp
I
TARGET+1
I
TARGET
Injection of cached
Target Instruction
I
n
Cache Jmp
I
I
TARGET+2
TARGET+1
I
TARGET
2001-04-19
C161U