SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 64

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

Data Sheet
Table 9
Execution from the internal RAM provides flexibility in terms of loadable and modifyable
code on the account of execution time.
Execution from external memory strongly depends on the selected bus mode and the
programming of the bus cycles (waitstates).
The operand and instruction accesses listed below can extend the execution time of an
instruction:
• Internal RAM operand reads via indirect addressing modes
• Internal SFR operand reads immediately after writing
• External operand reads
• External operand writes
• Jumps to non-aligned double word instructions in the internal ROM space
• Testing Branch Conditions immediately after PSW writes
5.4
The core CPU requires a set of Special Function Registers (SFRs) to maintain the
system state information, to supply the ALU with register-addressable constants and to
control system and bus configuration, multiply and divide ALU operations, code memory
segmentation, data memory paging, and accesses to the General Purpose Registers
and the System Stack.
The access mechanism for these SFRs in the CPU core is identical to the access
mechanism for any other SFR. Since all SFRs can simply be controlled by means of any
instruction, which is capable of addressing the SFR memory space, a lot of flexibility has
been gained, without the need to create a set of system-specific instructions.
Note, however, that there are user access restrictions for some of the CPU core SFRs
to ensure proper processor operations. The instruction pointer IP and code segment
pointer CSP cannot be accessed directly at all. They can only be changed indirectly via
branch instructions.
Memory Area
Internal RAM
16-bit Demux Bus
16-bit Mux Bus
8-bit Demux Bus
8-bit Mux Bus
CPU Special Function Registers
Minimum Execution Times
Instruction Fetch
Word
Instruction
6
2
3
4
6
64
Doubleword
Instruction
8
4
6
8
12
Word Operand Access
Read from
0/1
2
3
4
6
Central Processor Unit
Write to
0
2
3
4
6
2001-04-19
C161U