SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 74

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SAF-C161U-LF V1.3

Manufacturer Part Number
SAF-C161U-LF V1.3
Description
IC MCU ISDN 16BIT TTL TQFP-100
Manufacturer
Infineon Technologies
Series
C16xxr
Datasheet

Specifications of SAF-C161U-LF V1.3

Core Processor
C166
Core Size
16-Bit
Speed
36MHz
Connectivity
EBI/EMI, SPI, UART/USART, USB
Peripherals
POR, PWM, WDT
Number Of I /o
56
Program Memory Type
ROMless
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Other names
SAFC161ULFV1.3X
SAFC161ULFV13XP
SP000007502
Data Sheet
Figure 16
Note: When segmentation is disabled, the IP value is used directly as the 16-bit address.
Data Page Pointers DPP0, DPP1, DPP2, DPP3
These four non-bit addressable registers select up to four different data pages being
active simultaneously at run-time. The lower 10 bits of each DPP register select one of
the 1024 possible 16-Kbyte data pages while the upper 6 bits are reserved for future use.
The DPP registers allow to access the entire memory space in pages of 16 Kbytes each.
The DPP registers are implicitly used, whenever data accesses to any memory location
are made via indirect or direct long 16-bit addressing modes (except for override
accesses via EXTended instructions and PEC data transfers). After reset, the Data Page
Pointers are initialized in a way that all indirect or direct long 16-bit addresses result in
identical 18-bit addresses. This allows to access data pages 3...0 within segment 0 as
shown in the figure below. If the user does not want to use any data paging, no further
action is required.
Code Segment
255
254
0
1
Addressing via the Code Segment Pointer
FF’FFFF H
FE’0000 H
01’0000 H
00’0000 H
15
CSP Register
24/20/18-Bit Physical Code Address
74
0
15
Central Processor Unit
IP Register
MCA02265
2001-04-19
0
C161U

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