SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 379

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

• Execution of one PEC Transfer and resumption of Sleep mode will be selected if
• Continuation with standard Idle mode as configured with register SYSCON3 if
As wakeup from Idle mode, wakeup from Sleep mode is performed with any enabled
interrupt request. Sleep mode is terminated and the before selected (and above
described) continuation of processing is executed, if one of the following interrupts occur:
• Fast External Interrupts (EXxINT). All fast external interrupts can be selected for
• Alternate sources for Fast External Interrupts (EXxINT) as defined by the EXISEL
• RTC Timer T14 cyclic interrupt. For waking up from Sleep mode via RTC T14
• RTC interrupt(s). With new real time clock, additional RTC interrupts can be enabled
• Non-Maskable Interrupt NMI. A high-to-low transition on NMI pin always terminates
Setup Lengthening Control (Start Delay)
Contrary to Idle mode, after wakup from Sleep mode at first the ramp-up of clock system
(oscillator and PLL) has to be controlled before any CPU operation can be started. Only
when the clock system is locked on configured frequency, the following processing is
identical to wakeup from Idle mode.
Data Sheet
the interrupt is enabled by global (in PSW) and by individual (interrupt control register)
enable bit, and the CPU priority level of IDLE instruction is lower than the interrupt
level, thus the enabled interrupt has highest priority. Additionally, PEC Transfer for this
interrupt is enabled.
the interrupt is not enabled with the individual Interrupt Enable flag in its interrupt
control register. Note: In standard Idle mode the watchdog timer has to be serviced.
For description of SYSCON3 see ´description of Peripheral Management Module.
wakeup from Sleep mode by defining the related trigger transitions (edges) in the
EXICON register. All transition types are allowed also in Sleep mode.
register. If selected, transitions on receive lines of serial interface controllers (ASC,
SSC, USB) can be used for wakeup from Sleep mode.
interrupt, the RTC operation during Sleep mode must be selected in bitfield
SLEEPCON within register SYSCON1. Additionally, the RTC interrupt must be
enabled in the Interrupt Subnode Control register ISNC.
via the Interrupt Subnode Control register RTCISNC. For wakeup, RTC operation
during Sleep mode must be selected in SYSCON1. This function is not supported in
C167CS.
the Sleep mode. The NMI input is filtered for spike suppression. (Planned: Input
signals shorter than 10ns are suppressed, detection is guaranteed for minimum 150ns
NMI signal).
379
Power Reduction Modes
2001-04-19
C161U