SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 370

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

Data Sheet
the C161U even for the first code fetch after reset. The two bits are copied into bit field
BTYP of register BUSCON0. P0L.7 controls the data bus width, while P0L.6 controls the
address output (multiplexed or demultiplexed). This bit field may be changed via
software after reset, if required.
PORT0 and PORT1 are automatically switched to the selected bus mode. In multiplexed
bus modes PORT0 drives both the 16-bit intra-segment address and the output data,
while PORT1 remains in high impedance state as long as no demultiplexed bus is
selected via one of the BUSCON registers. In demultiplexed bus modes PORT1 drives
the 16-bit intra-segment address, while PORT0 or P0L (according to the selected data
bus width) drives the output data.
For a 16-bit data bus BHE is automatically enabled, for an 8-bit data bus BHE is disabled
via bit BYTDIS in register SYSCON.
Default: 16-bit data bus with multiplexed addresses.
Note: If an internal start is selected via pin EA, these two pins are disregarded and bit
Write Configuration
Pin P0H.0 (WRC) selects the initial operation of the control pins WR and BHE during
reset. When high, this pin selects the standard function, ie. WR control and BHE. When
low, it selects the alternate configuration, ie. WRH and WRL. Thus even the first access
after a reset can go to a memory controlled via WRH and WRL. This bit is latched in
register RP0H and its inverted value is copied into bit WRCFG in register SYSCON.
Default: Standard function (WR control and BHE).
Chip Select Lines
Pins P0H.2 and P0H.1 (CSSEL) define the number of active chip select signals during
reset. This allows the selection which pins of Port 6 drive external CS signals and which
are used for general purpose IO. The two bits are latched in register RP0H.
Default: All 4 chip select lines active (CS3...CS0).
Note: The selected number of CS signals cannot be changed via software after reset.
BTYP
Encoding
0 0
0 1
1 0
1 1
field BTYP of register BUSCON0 is cleared.
External Data Bus Width
8-bit Data
8-bit Data
16-bit Data
16-bit Data
370
External Address Bus Mode
Demultiplexed Addresses
Multiplexed Addresses
Demultiplexed Addresses
Multiplexed Addresses
System Reset
2001-04-19
C161U