SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 66

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

Data Sheet
SYSCON (FF12
Bit
XPER-
SHARE
VISIBLE
XPEN
OSCENBL
CSCFG
WRCFG
CLKEN
BYTDIS
15
STKSZ
14
rw
13
H
Function
Reserved
The XPER-SHARE mode, known from other C16x Infineon derivatives,
is not supported in the C161U. This bit must be set to ’0’ signal.
Visible Mode Control
’0’:
’1’:
XBUS Peripheral Enable Bit
’0’:
’1’:
Note: This bit is valid only for derivatives that contain X-Peripherals.
Oscillator Watchdog Enable Bit
‘0’:
‘1’:
Chip Select Configuration Control
‘0’:
‘1’:
Write Configuration Control (Set according to pin P0H.0 during reset)
’0’:
’1’:
System Clock Output Enable (CLKOUT)
’0’:
’1’:
Disable/Enable Control for Pin BHE (Set according to data bus width)
’0’:
’1’:
/ 89
ROM
S1
12
rw
H
)
SGT
DIS
Accesses to XBUS peripherals are done internally
XBUS peripheral accesses are made visible on the external pins
Accesses to the on-chip X-Peripherals and their functions are
disabled
The on-chip X-Peripherals are enabled and can be accessed
The oscillator watchdog is disabled. Default configuration.
The oscillator watchdog is enabled.
Latched CS mode. The CS signals are latched internally and
driven to the enabled port pins synchronously.
Unlatched CS mode. The CS signals are directly derived from
the address and driven to the enabled port pins.
Pins WR and BHE retain their normal function
Pin WR acts as WRL, pin BHE acts as WRH
CLKOUT disabled: pin may be used for general purpose I/O
CLKOUT enabled: pin outputs the system clock signal
Pin BHE enabled
Pin BHE disabled, pin may be used for general purpose I/O
11
rw
ROM
EN
10
rw
BYT
DIS
rw
9
CLK
EN
rw
8
SFR
66
CFG
WR
rw
7
CFG
CS
rw
6
5
-
-
ENBL
OSC
rw
4
Central Processor Unit
Reset Value: 0XX0
3
-
-
XPEN
rw
2
BLE
VISI
rw
2001-04-19
1
C161U
SHARE
XPER-
rw
0
H