SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 55

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

The on-chip peripheral units of the C161U work nearly independent of the CPU with a
separate clock generator. Data and control information is interchanged between the
CPU and these peripherals via Special Function Registers (SFRs). Whenever
peripherals need a non-deterministic CPU action, an on-chip Interrupt Controller
compares all pending peripheral service requests against each other and prioritizes one
of them. If the priority of the current CPU operation is lower than the priority of the
selected peripheral request, an interrupt will occur.
Basically, there are two types of interrupt processing:
• Standard interrupt processing forces the CPU to save the current program status and
• PEC interrupt processing steals just one machine cycle from the current CPU activity
System errors detected during program execution (socalled hardware traps) or an
external non-maskable interrupt are also processed as standard interrupts with a very
high priority.
In contrast to other on-chip peripherals, there is a closer conjunction between the
watchdog timer and the CPU. If enabled, the watchdog timer expects to be serviced by
the CPU within a programmable period of time, otherwise it will reset the chip. Thus, the
watchdog timer is able to prevent the CPU from going totally astray when executing
erroneous code. After reset, the watchdog timer starts counting automatically, but it can
be disabled via software, if desired.
Beside its normal operation there are the following particular CPU states:
• Reset state: Any reset (hardware, software, watchdog) forces the CPU into a
• IDLE state: The clock signal to the CPU itself is switched off, while the clocks for the
• POWER DOWN state: All of the on-chip clocks are switched off.
A transition into an active CPU state is forced by an interrupt (if being IDLE) or by a reset
(if being in POWER DOWN mode).
The IDLE, POWER DOWN and RESET states can be entered by particular C161U
system control instructions.
A set of Special Function Registers is dedicated to the functions of the CPU core:
• General System Configuration
• CPU Status Indication and Control
• Code Access Control
• Data Paging Control
• GPRs Access Control
• System Stack Access Control
• Multiply and Divide Support
• ALU Constants Support
Data Sheet
the return address on the stack before branching to the interrupt vector jump table.
to perform a single data transfer via the on-chip Peripheral Event Controller (PEC).
predefined active state.
on-chip peripherals keep running.
55
MDL, MDH, MDC
ZEROS, ONES
SYSCON (RP0H)
PSW
IP, CSP
CP
DPP0, DPP1, DPP2, DPP3
SP, STKUN, STKOV
Central Processor Unit
2001-04-19
C161U