SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 399

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

The above save sequence and the restore sequence after COPYL are only required if
the current routine could have interrupted a previous routine which contained a MUL or
DIV instruction. Register MDC is also saved because it is possible that a previous
routine's Multiply or Divide instruction was interrupted while in progress. In this case the
information about how to restart the instruction is contained in this register. Register
MDC must be cleared to be correctly initialized for a subsequent multiplication or
division. The old MDC contents must be popped from the stack before the RETI
instruction is executed.
For a division the user must first move the dividend into the MD register. If a 16/16-bit
division is specified, only the low portion of register MD must be loaded. The result is also
stored into register MD. The low portion (MDL) contains the integer result of the division,
while the high portion (MDH) contains the remainder.
The following instruction sequence performs a 32 by 16-bit division:
MOV
MOV
DIV
JMPR
MOV
MOV
Whenever a multiply or divide instruction is interrupted while in progress, the address of
the interrupted instruction is pushed onto the stack and the MULIP flag in the PSW of the
interrupting routine is set. When the interrupt routine is exited with the RETI instruction,
this bit is implicitly tested before the old PSW is popped from the stack. If MULIP=’1’ the
multiply/divide instruction is re-read from the location popped from the stack (return
address) and will be completed after the RETI instruction has been executed.
Note: The MULIP flag is part of the context of the interrupted task. When the
BCD Calculations
No direct support for BCD calculations is provided in the C161U. BCD calculations are
performed by converting BCD data to binary data, performing the desired calculations
using standard data types, and converting the result back to BCD data. Due to the
enhanced performance of division instructions binary data is quickly converted to BCD
data through division by 10
multiple bit shift instructions. This provides similar performance compared to instructions
directly supporting BCD data types, while no additional hardware is required.
Data Sheet
interrupting routine does not return to the interrupted task (eg. scheduler switches
to another task) the MULIP flag must be set or cleared according to the context of
the task that is switched to.
MDH, R1
MDL, R2
R3
cc_V, ERROR
R3, MDH
R4, MDL
D
. Conversion from BCD data to binary data is enhanced by
;Move low portion to MD
;Move dividend to MD register. Sets MDRIU
;Divide 32/16 signed, R3 holds divisor
;Test for divide overflow
;Move remainder to R3
;Move integer result to R4. Clears MDRIU
399
System Programming
2001-04-19
C161U