SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 378

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

Data Sheet
Note: Sleep mode cannot be entered in Slow Down mode - the start of sleep mode and
The Sleep mode is controlled by bitfield SLEEPCON within register SYSCON1.
SYSCON1 (F1DC
Note: SYSCON1 is write protected after the execution of EINIT unless it is released via
General description of SYSCON1 bits:
Before entering Sleep mode with the IDLE instruction, the continuation of instruction
processing after termination of Sleep mode must be prepared as known from standard
Idle mode. For wakeup with interrupt, four general possibilities of continuation can be
selected, which are controlled (prepared) as follows:
• Continuation with first instruction after the IDLE instruction will be enabled if
• Continuation with first instruction of dedicated interrupt service routine will be
Bit
SLEEPCON SLEEP Mode Configuration
15
-
-
– interrupts are globally disabled with the Interrupt Enable bit in PSW, or
– the interrupt is enabled by global (PSW) and by individual (interrupt control register)
selected if
the interrupt is enabled by global (in PSW) and by individual (interrupt control register)
enable bit, and the CPU priority level of IDLE instruction is lower than the interrupt
level, thus the enabled interrupt has highest priority. Additionally, PEC Transfer for this
interrupt is not enabled. The continuation with the dedicated service routine is always
performed in case of NMI hardware traps, independently of any enable bit or CPU
priority level.
enable bit, but the current CPU priority level (in PSW) of IDLE instruction is higher
than the interrupt level.
wakeup is only possible in the normal clocking mode (PLL or direct drive) as
defined with the startup configuration on port P0. If Sleep mode shall be entered
during Slow Down mode, automatically the standard Idle mode is selected as
configured with SYSCON3 register.
the unlock sequence.
14
-
-
13
-
-
Function
‘0 0’:
‘0 1’:
‘1 0’:
‘1 1’:
H
/ EE
12
-
-
H
)
11
normal IDLE mode
SLEEP mode with running RTC
reserved
SLEEP mode with stopped RTC and stopped OSC
-
-
10
-
-
9
-
-
8
-
-
ESFR-b
378
7
-
-
6
-
-
5
-
-
Power Reduction Modes
4
-
-
Reset Value: 0000
3
-
-
2
-
-
SLEEPCON
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1
C161U
H
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0