SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 441

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

Miscellaneous
• Null operation which requires 2 bytes of storage and the minimum time for execution:
• Definition of an unseparable instruction sequence: ATOMIC
• Switch ‘reg’, ‘bitoff’ and ‘bitaddr’ addressing modes to the Extended SFR space: EXTR
• Override the DPP addressing scheme using a specific data page instead of the DPPs,
• Override the DPP addressing scheme using a specific segment instead of the DPPs,
Note: The ATOMIC and EXT* instructions provide support for uninterruptable code
Protected Instructions
Some instructions of the C161U which are critical for the functionality of the controller
are implemented as so-called Protected Instructions. These protected instructions use
the maximum instruction format of 32 bits for decoding, while the regular instructions
only use a part of it (eg. the lower 8 bits) with the other bits providing additional
information like involved registers. Decoding all 32 bits of a protected doubleword
instruction increases the security in cases of data distortion during instruction fetching.
Critical operations like a software reset are therefore only executed if the complete
instruction is decoded without an error. This enhances the safety and reliability of a
microcontroller system.
Data Sheet
NOP
and optionally switch to ESFR space: EXTP, EXTPR
and optionally switch to ESFR space: EXTS, EXTSR
sequences eg. for semaphore operations. They also support data addressing
beyond the limits of the current DPPs (except ATOMIC), which is advantageous
for bigger memory models in high level languages. Refer to chapter “System
Programming” for examples.
441
Instruction Set Summary
2001-04-19
C161U