SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 309

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

C161U
High-Speed Synchronous Serial Interface
(SSCTIR) will be generated to indicate that SSCTB may be reloaded again. When the
programmed number of bits (2...16) has been transferred, the contents of the shift
register are moved to the Receive Buffer SSCRB and a receive interrupt request
(SSCRIR) will be generated. If no further transfer is to take place (SSCTB is empty),
SSCBSY will be cleared at the same time. Software should not modify SSCBSY, as this
flag is hardware controlled.
Note: Only one SSC (etc.) can be master at a given time.
The transfer of serial data bits can be programmed in many respects:
• the data width can be chosen from 2 bits to 16 bits
• transfer may start with the LSB or the MSB
• the shift clock may be idle low or idle high
• data bits may be shifted with the leading or trailing edge of the clock signa
• the baudrate may be set from 274.7 Baud up to 18 MBaud (@ 36 MHz CPU clock)
• the shift clock can be generated (master) or received (slave)
This allows the adaptation of the SSC to a wide range of applications, where serial data
transfer is required.
Data Width Selection supports the transfer of frames of any length, from 2-bit
“characters” up to 16-bit “characters”. Starting with the LSB (SSCHB=’0’) allows
communication eg. with ASC devices in synchronous mode (C166 family) or 8051 like
serial interfaces. Starting with the MSB (SSCHB=’1’) allows operation compatible with
the SPI interface.
Regardless which data width is selected and whether the MSB or the LSB is transmitted
first, the transfer data is always right aligned in registers SSCTB and SSCRB, with the
LSB of the transfer data in bit 0 of these registers. The data bits are rearranged for
transfer by the internal shift register logic. The unselected bits of SSCTB are ignored, the
unselected bits of SSCRB will be not valid and should be ignored by the receiver service
routine.
Clock Control allows the adaptation of transmit and receive behaviour of the SSC to a
variety of serial interfaces. A specific clock edge (rising or falling) is used to shift out
transmit data, while the other clock edge is used to latch in receive data. Bit SSCPH
selects the leading edge or the trailing edge for each function. Bit SSCPO selects the
level of the clock line in the idle state. So for an idle-high clock the leading edge is a
falling one, a 1-to-0 transition. The figure below is a summary.
Data Sheet
309
2001-04-19