SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 411

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SAF-C161U-LF V1.3

Manufacturer Part Number
SAF-C161U-LF V1.3
Description
IC MCU ISDN 16BIT TTL TQFP-100
Manufacturer
Infineon Technologies
Series
C16xxr
Datasheet

Specifications of SAF-C161U-LF V1.3

Core Processor
C166
Core Size
16-Bit
Speed
36MHz
Connectivity
EBI/EMI, SPI, UART/USART, USB
Peripherals
POR, PWM, WDT
Number Of I /o
56
Program Memory Type
ROMless
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Other names
SAFC161ULFV1.3X
SAFC161ULFV13XP
SP000007502
C161U
System Programming
Enabling and Disabling the Internal Code Memory After Reset
If the internal code memory does not contain an appropriate startup code, the system
may be booted from external memory, while the internal memory is enabled afterwards
to provide access to library routines, tables, etc.
If the internal code memory only contains the startup code and/or test software, the
system may be booted from internal memory, which may then be disabled, after the
software has switched to executing from (eg.) external memory, in order to free the
address space occupied by the internal code memory, which is now unnecessary.
21.10
Pits, Traps and Mines
Although handling the internal code memory provides powerful means to enhance the
overall performance and flexibility of a system, extreme care must be taken in order to
avoid a system crash. Instruction memory is the most crucial resource for the C161U and
it must be made sure that it never runs out of it. The following precautions help to take
advantage of the methods mentioned above without jeopardizing system security.
General Rules
When mapping the code memory no instruction or data accesses should be made to the
internal memory, otherwise unpredictable results may occur.
To avoid these problems, the instructions that configure the internal code memory
should be executed from external memory or from the on-chip RAM.
Whenever the internal code memory is disabled, enabled or remapped the DPPs must
be explicitly (re)loaded to enable correct data accesses to the internal and/or external
memory.
Data Sheet
411
2001-04-19

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