SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 76

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

Data Sheet
In case of the segmented memory mode the selected number of segment address bits
(via bitfield SALSEL) of the respective DPP register is output on the respective segment
address pins of Port 4 for all external data accesses.
A DPP register can be updated via any instruction, which is capable of modifying an
SFR.
Note: Due to the internal instruction pipeline, a new DPP value is not yet usable for the
Figure 17
Context Pointer CP
This non-bit addressable register is used to select the current register context. This
means that the CP register value determines the address of the first General Purpose
Register (GPR) within the current register bank of up to 16 wordwide and/or bytewide
GPRs.
Data Pages
Affer reset or with segmentation disabled the DPP registers select data pages 3...0.
All of the internal memory is accessible in these cases.
1023
1022
1021
operand address calculation of the instruction immediately following the
instruction updating the DPP register.
3
2
0
1
Addressing via the Data Page Pointers
DPP Registers
76
DPP3-11
DPP2-10
DPP1-01
DPP0-00
15 14
16-Bit Data Address
Central Processor Unit
14-Bit
Intra-Page Address
(concatenated with
content of DPPx).
MCA02264
2001-04-19
C161U
0