SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 79

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SAF-C161U-LF V1.3

Manufacturer Part Number
SAF-C161U-LF V1.3
Description
IC MCU ISDN 16BIT TTL TQFP-100
Manufacturer
Infineon Technologies
Series
C16xxr
Datasheet

Specifications of SAF-C161U-LF V1.3

Core Processor
C166
Core Size
16-Bit
Speed
36MHz
Connectivity
EBI/EMI, SPI, UART/USART, USB
Peripherals
POR, PWM, WDT
Number Of I /o
56
Program Memory Type
ROMless
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Other names
SAFC161ULFV1.3X
SAFC161ULFV13XP
SP000007502
Short 8-Bit Register Addresses (mnemonic: reg or bitoff) within a range from F0
FF
most significant bits are ignored. The respective physical GPR address calculation is
identical to that for the short 4-bit GPR addresses. For single bit accesses on a GPR, the
GPR's word address is calculated as just described, but the position of the bit within the
word is specified by a separate additional 4-bit value.
Figure 19
Stack Pointer SP
This non-bit addressable register is used to point to the top of the internal system stack
(TOS). The SP register is pre-decremented whenever data is to be pushed onto the
stack, and it is post-incremented whenever data is to be popped from the stack. Thus,
the system stack grows from higher toward lower memory locations.
Since the least significant bit of register SP is tied to '0' and bits 15 through 12 are tied
to '1' by hardware, the SP register can only contain values from F000
allows to access a physical stack within the internal RAM of the C161U. A virtual stack
(usually bigger) can be realized via software. This mechanism is supported by registers
STKOV and STKUN (see respective descriptions below).
The SP register can be updated via any instruction, which is capable of modifying an
SFR.
Note: Due to the internal instruction pipeline, a POP or RETURN instruction must not
Data Sheet
Control
H
interpret the four least significant bits as short 4-bit GPR address, while the four
immediately follow an instruction updating the SP register.
Implicit CP Use by Short GPR Addressing Modes
Context
Pointer
Specified by reg or bitoff
For byte GPR
1111
+
accesses
4-Bit GPR
Address
2 *
For word GPR
79
accesses
Central Processor Unit
Internal
GPRs
RAM
H
to FFFE
2001-04-19
Must be
within the
internal
RAM area
MCD02005
C161U
H
. This
H
to

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