SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 120

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

Data Sheet
7.5
Before an interrupt request that has been arbitrated is actually serviced, the status of the
current task is automatically saved on the system stack. The CPU status (PSW) is saved
along with the location, where the execution of the interrupted task is to be resumed after
returning from the service routine. This return location is specified through the Instruction
Pointer (IP) and, in case of a segmented memory model, the Code Segment Pointer
(CSP). Bit SGTDIS in register SYSCON controls, how the return location is stored.
The system stack receives the PSW first, followed by the IP (unsegmented) or followed
by CSP and then IP (segmented mode). This optimizes the usage of the system stack,
if segmentation is disabled.
The CPU priority field (ILVL in PSW) is updated with the priority of the interrupt request
that is to be serviced, so the CPU now executes on the new level. If a multiplication or
division was in progress at the time the interrupt request was acknowledged, bit MULIP
in register PSW is set to ‘1’. In this case the return location that is saved on the stack is
not the next instruction in the instruction flow, but rather the multiply or divide instruction
itself, as this instruction has been interrupted and will be completed after returning from
the service routine.
Figure 23
The interrupt request flag of the source that is being serviced is cleared. The IP is loaded
with the vector associated with the requesting source (the CSP is cleared in case of
segmentation) and the first instruction of the service routine is fetched from the
respective vector location, which is expected to branch to the service routine itself. The
data page pointers and the context pointer are not affected.
SP
a)
System Stack before
Interrupt Entry
Saving the Status during Interrupt Service
--
--
--
Task Status saved on the System Stack
Addresses
Addresses
High
Low
SP
b)
System Stack after
Interrupt Entry
(Unsegmented)
PSW
120
IP
--
Interrupted
Status of
Interrupt and Trap Functions
Task
c)
System Stack after
Interrupt Entry
(Segmented)
PSW
CSP
IP
2001-04-19
C161U
MCD02226
SP