SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 84

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

Data Sheet
MDC (FF0E
When a division or multiplication was interrupted before its completion and the multiply/
divide unit is required, the MDC register must first be saved along with registers MDH
and MDL (to be able to restart the interrupted operation later), and then it must be
cleared prepare it for the new calculation. After completion of the new division or
multiplication, the state of the interrupted multiply or divide operation must be restored.
The MDRIU flag is the only portion of the MDC register which might be of interest for the
user. The remaining portions of the MDC register are reserved for dedicated use by the
hardware, and should never be modified by the user in another way than described
above. Otherwise, a correct continuation of an interrupted multiply or divide operation
cannot be guaranteed.
A detailed description of how to use the MDC register for programming multiply and
divide algorithms can be found in chapter “System Programming”.
Constant Zeros Register ZEROS
All bits of this bit-addressable register are fixed to '0' by hardware. This register can be
read only. Register ZEROS can be used as a register-addressable constant of all zeros,
ie. for bit manipulation or mask generation. It can be accessed via any instruction, which
is capable of addressing an SFR.
Bit
MDRIU
!!
15
-
-
14
-
-
H
/ 87
13
-
-
Function
Multiply/Divide Register In Use
‘0’:
‘1’:
Internal Machine Status
The multiply/divide unit uses these bits to control internal operations.
Never modify these bits without saving and restoring register MDC.
H
)
12
-
-
Cleared, when register MDL is read via software.
Set when register MDL or MDH is written via software, or when
a multiply or divide instruction is executed.
11
-
-
10
-
-
9
-
-
8
-
-
SFR
84
r(w)
!!
7
r(w)
!!
6
r(w)
!!
5
MDR
r(w)
IU
4
Central Processor Unit
r(w)
Reset Value: 0000
3
!!
r(w)
!!
2
r(w)
2001-04-19
!!
1
C161U
r(w)
!!
0
H