SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 109

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

Note: The X-Bus interrupts xb(0) and xb(1), known from C16x device’s, are connected
Note: Each entry of the interrupt vector table provides space for two word instructions or
Note: One interrupt control register is provided for each interrupt node. All IC registers
Table 22 lists the vector locations for hardware traps and the corresponding status flags
in register TFR. It also lists the priorities of trap service for cases, where more than one
trap condition might be detected within the same instruction. After any reset (hardware
reset, software reset instruction SRST, or reset by watchdog timer overflow) program
execution starts at the reset vector at location 00’0000
over every other system activity and therefore have the highest priority (trap priority III).
Software traps may be initiated to any vector location between 00’0000
A service routine entered via a software TRAP instruction is always executed on the
current CPU priority level which is indicated in bit field ILVL in register PSW. This means
that routines entered via the software TRAP instruction can be interrupted by all
hardware traps or higher level interrupt requests.
Table 22
Data Sheet
Exception Condition
Reset Functions:
Class A Hardware Traps:
Hardware Reset
Software Reset
Watchdog Timer
Overflow
Non-Maskable Interrupt
Stack Overflow
Stack Underflow
Debug Trap
to the main interrupt node of the respective X-Bus peripheral: UTXRINT (xb(0) and
irq(22)) and EPECINT (xb(1) and irq(40).
one doubleword instruction. The respective vector location results from multiplying
the trap number by 4 (4 bytes per entry).
of the C161U can be found in the SFR list.
Hardware Traps and Vector Locations
Trap
Flag
NMI
STKOF
STKUF
DEBUG
109
Trap
Vector
RESET
RESET
RESET
NMITRAP
STOTRAP
STUTRAP
DEBTRAP
H
. Reset conditions have priority
Interrupt and Trap Functions
Vector
Location
00’0000
00’0000
00’0000
00’0008
00’0010
00’0018
00’0020
H
H
H
H
H
H
H
Trap
Number
00
00
00
02
04
06
08
H
and 00’01FC
H
H
H
H
H
H
H
2001-04-19
C161U
Trap
Prio.
III
III
III
II
II
II
II
H
.