SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 112

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

Data Sheet
decrements to zero. This allows a normal CPU interrupt to respond to a completed PEC
block transfer.
Note: Modifying the Interrupt Request flag via software causes the same effects as if it
Interrupt Priority Level and Group Level
The four bits of bit field ILVL specify the priority level of a service request for the
arbitration of simultaneous requests. The priority increases with the numerical value of
ILVL, so 0000
When more than one interrupt request on a specific level gets active at the same time,
the values in the respective bit fields GLVL are used for second level arbitration to select
one request for being serviced. Again the group priority increases with the numerical
value of GLVL, so 00
Note: All interrupt request sources that are enabled and programmed to the same
Upon entry into the interrupt service routine, the priority level of the source that won the
arbitration and who’s priority level is higher than the current CPU level, is copied into bit
field ILVL of register PSW after pushing the old PSW contents on the stack.
The interrupt system of the C161U allows nesting of up to 15 interrupt service routines
of different priority levels (level 0 cannot be arbitrated).
Interrupt requests that are programmed to priority levels 15 or 14 (ie, ILVL=111X
be serviced by the PEC, unless the COUNT field of the associated PECC register
contains zero. In this case the request will instead be serviced by normal interrupt
processing. Interrupt requests that are programmed to priority levels 13 through 1 will
always be serviced by normal interrupt processing.
Note: Priority level 0000
For interrupt requests which are to be serviced by the PEC, the associated PEC channel
number is derived from the respective ILVL (LSB) and GLVL (see figure below). So
programming a source to priority level 15 (ILVL=1111
7...4, programming a source to priority level 14 (ILVL=1110
group 3...0. The actual PEC channel number is then determined by the group priority
field GLVL.
had been set or cleared by hardware.
priority level must always be programmed to different group priorities. Otherwise
an incorrect interrupt vector will be generated.
will never be serviced, because it can never interrupt the CPU. However, an
enabled interrupt request on level 0000
reactivate the CPU.
B
is the lowest and 1111
B
is the lowest and 11
B
is the default level of the CPU. Therefore a request on level 0
B
is the highest priority level.
112
B
is the highest group priority.
B
will terminate the C161U’s Idle mode and
B
) selects the PEC channel group
Interrupt and Trap Functions
B
) selects the PEC channel
2001-04-19
C161U
B
) will