SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 192

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SAF-C161U-LF V1.3

Manufacturer Part Number
SAF-C161U-LF V1.3
Description
IC MCU ISDN 16BIT TTL TQFP-100
Manufacturer
Infineon Technologies
Series
C16xxr
Datasheet

Specifications of SAF-C161U-LF V1.3

Core Processor
C166
Core Size
16-Bit
Speed
36MHz
Connectivity
EBI/EMI, SPI, UART/USART, USB
Peripherals
POR, PWM, WDT
Number Of I /o
56
Program Memory Type
ROMless
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Other names
SAFC161ULFV1.3X
SAFC161ULFV13XP
SP000007502
Data Sheet
Figure 51
The read/write delay is controlled via the RWDCx bits in the BUSCON registers. The
command(s) will be delayed, if bit RWDCx is ‘0’ (default after reset).
Early WR Signal Deactivation
The duration of an external write access can be shortened by one TCL. The WR signal
is activated (driven low) in the standard way, but can be deactivated (driven high) one
TCL earlier than defined in the standard timing. In this case, also the data output drivers
will be deactivated one TCL earlier.
This is especially useful in systems which operate on higher CPU clock frequencies and
employ external modules (memories, peripherals, etc.) which switch on their own data
drivers very fast in response to e.g. a chip select signal.
Conflicts between the C161U and the external peripheral’s output drivers can be avoided
then by selecting early WR for the C161U.
Note: Make sure that the reduced WR low time then still matches the requirements of
Segment
BUS (P0)
BUS (P0)
1)
The Data drivers from the previous bus cycle should be disabled when the RD signal becomes active.
the external peripheral/memory.
ALE
WR
RD
Read/Write Delay
Address
Read/Write
Delay
1)
192
Bus Cycle
Address
Data/Instr.
Data
External Bus Interface
2001-04-19
MCT02066
C161U

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