SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 195

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

C161U
External Bus Interface
10.4
Controlling the External Bus Controller
A set of registers controls the functions of the EBC. General features like the usage of
interface pins (WR, BHE), segmentation are controlled via register SYSCON.
Note: For SYSCON register description, refer to page 66.
The properties of a bus cycle like chip select mode, usage of READY, length of ALE,
external bus mode, read/write delay and waitstates are controlled via registers
BUSCON4...BUSCON0. Four of these registers (BUSCON4...BUSCON1) have an
address select register (ADDRSEL4...ADDRSEL1) associated with them, which allows
to specify up to four address areas and the individual bus characteristics within these
areas. All accesses that are not covered by these four areas are then controlled via
BUSCON0. This allows to use memory components or peripherals with different
interfaces within the same system, while optimizing accesses to each of them.
The layout of the five BUSCON registers is identical. Registers BUSCON4...BUSCON1,
which control the selected address windows, are completely under software control,
while register BUSCON0, which eg. is also used for the very first code access after reset,
is partly controlled by hardware, ie. it is initialized via PORT0 during the reset sequence.
This hardware control allows to define an appropriate external bus for systems, where
no internal program memory is provided.
Data Sheet
195
2001-04-19