SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 325

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

location by the EPEC injecting MOV-instructions into the decode stage of the instruction
pipeline.
In both directions the SW will control the EPEC providing DMA-like source and
destination pointers on a per-packet basis. This provides a maximum degee of flexibility
for the application SW, e.g. a linked list structure or circular FIFOs implementation with
buffer pool elements can be used.
IN-Transactions (Device to Host: TX)
The host requests device data by using the IN transaction. The IN transaction
mechanism handled by the device HW/SW is shown in Figure 103 below.
Figure 103
Since the UDC requests data handshake from the application within 1UDC clock cycle
(@12MHz) the SW has to provide the next data packet to the Transmit FIFO in time, i.e.
before the host is requesting data, in order to prevent the FIFO from starvation resulting
in a NACK to the host. This can be achieved by either polling for the USBD_TXDONEn
for bit being asserted, indicating a free FIFO or by providing the next packet as soon as
the previous packet has been transmitted completely using the interrupt
USBD_INT_TXDONE directly.
Zero-data-length packets can be sent from SW to the host by writing into the TxEOD
register.
Data Sheet
Set EPEC_START
Enable EPEC
= ’1’
USB IN-Transfer controlled by SW
USBD_INT_TX_DONE
ISR active
from USBD
IDLE
ByteCount, SrcPtr,
USBD_INT_TX_DONE
program EPEC:
325
DestPtr
Polling active
Poll
USBD_INT_TX_DONE
Transmission
Timeout Error
= ’1’
Timer expired
Transmit FIFO
USB Interface Controller
Ready
USBD_INT_TX_DONE
busy with
previous packet
EPEC or FIFO
= ’0’
Reset
2001-04-19
C161U