SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 397

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

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To aid in software development, a number of features has been incorporated into the
instruction set of the C161U, including constructs for modularity, loops, and context
switching. In many cases commonly used instruction sequences have been simplified
while providing greater flexibility. The following programming features help to fully utilize
this instruction set.
Instructions Provided as Subsets of Instructions
In many cases, instructions found in other microcontrollers are provided as subsets of
more powerful instructions in the C161U. This allows the same functionality to be
provided while decreasing the hardware required and decreasing decode complexity. In
order to aid assembly programming, these instructions, familiar from other
microcontrollers, can be built in macros, thus providing the same names.
Directly Substitutable Instructions are instructions known from other microcontrollers
that can be replaced by the following instructions of the C161U:
Modification of System Flags is performed using bit set or bit clear instructions (BSET,
BCLR ). All bit and word instructions can access the PSW register, so no instructions like
CLEAR CARRY or ENABLE INTERRUPTS are required.
External Memory Data Access does not require special instructions to load data
pointers or explicitly load and store external data. C161U provides a Von-Neumann
memory architecture and its on-chip hardware automatically detects accesses to internal
RAM, GPRs, and SFRs.
Multiplication and Division
Multiplication and division of words and double words is provided through multiple cycle
instructions implementing a Booth algorithm. Each instruction implicitly uses the 32-bit
register MD (MDL = lower 16 bits, MDH = upper 16 bits). The MDRIU flag (Multiply or
Divide Register In Use) in register MDC is set whenever either half of this register is
written to or when a multiply/divide instruction is started. It is cleared whenever the MDL
register is read. Because an interrupt can be acknowledged before the contents of
register MD are saved, this flag is required to alert interrupt routines, which require the
Data Sheet
Substituted Instruction
CLR
CPLB
DEC
INC
SWAPB
System Programming
Rn
Bit
Rn
Rn
Rn
C161U Instruction
AND
BMOVN
SUB
ADD
ROR
Rn, #0
Bit, Bit
Rn, #1
Rn, #1
Rn, #8
397
H
H
H
H
Function
Clear register
Complement bit
Decrement register
Increment register
Swap bytes within word
System Programming
2001-04-19
C161U