SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 85

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

ZEROS (FF1C
Constant Ones Register ONES
All bits of this bit-addressable register are fixed to '1' by hardware. This register can be
read only. Register ONES can be used as a register-addressable constant of all ones,
ie. for bit manipulation or mask generation. It can be accessed via any instruction, which
is capable of addressing an SFR.
ONES (FF1E
5.5
Introduction
Compared to existing C16x architecture, the PEC transfer function is enhanced by
extended functionality. The extended PEC function is a further step into DMA control
functionality. It especially supports integrated system design with XBUS as system bus.
Note: The device address decoding structure is always based on 24-bit addresses. But
The extended PEC functions are defined as follows:
– Source pointer and destination pointer are extended to 24-bit pointer, thus enabling
– Two of the PEC channels are expanded by additional 16-bit transfer count registers;
– For always two channels a chaining feature is provided. When enabled in the PEC
Data Sheet
15
15
0
1
r
r
PEC controlled data transfer between any two locations within the total address
space. Both 8-bit segment numbers of every source/destination pointer pair are
defined in one 16-bit SFR register; thus, 8 PEC segment number registers are
available for the 8 PEC channels.
when enabled, the original 8-bit bytecount in the control register serves as package
length count, thus defining the amount of bytes or words to be transferred with one
request. In C161U the package size is always limited to one transfer.
control register, a termination interrupt of one channel will automatically switch
transfer control to the other channel of the channel pair.
due to the limited number of port P4 pins, only the address bits A20:A16 can be
made visible on the external X-Bus interface.
14
14
0
1
r
r
PEC - Extension of Functionality
H
13
13
0
1
r
r
H
/ 8F
/ 8E
H
12
12
)
0
1
H
r
r
)
11
11
0
1
r
r
10
10
0
1
r
r
9
0
9
1
r
r
8
0
8
1
r
r
SFR
SFR
85
7
0
7
1
r
r
6
0
6
1
r
r
5
0
5
1
r
r
4
0
4
1
r
r
Central Processor Unit
Reset Value: 0000
3
0
Reset Value: FFFF
3
1
r
r
2
0
2
1
r
r
2001-04-19
1
0
1
1
r
r
C161U
0
0
0
1
r
r
H
H