SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 203

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

XBCON/2/3 (F114
Note: The ’BUSCON switch control’ BSWC is a new function, which is necessary due to
Data Sheet
Bit
MCTCx
RWDCx
MTTCx
BTYPx
EWENx
ALECTLx
BUSACTx*
BSWCx
RDYENx
15
-
-
the execution with higher frequencies, to avoid bus collisions on data bus in case
of peripheral change (see BUSCON).
14
-
-
13
-
-
Early Write Enable
Bus Active Control
READY Enable
Function
Memory Cycle Time Control (see BUSCON)
READ/WRITE Delay Control (see BUSCON)
Memory Tri-state Time Control (see BUSCON)
Bus Type Selection; only demultiplexed busses are supported on
XBUS;
’00’: 8 bit bus
’10’: 16 bit bus;
’0’: Standard write enable signal control
’1’: Write active state is disabled one TCL earlier
ALE Lengthening Control Bit (see BUSCON)
‘0’: XBUS (peripheral) disabled
‘1’: XBUS (peripheral) enabled
Enables the XBUS and the according chip select XCSx for the respective
address window (respective XBUS peripheral), selected with according
XADRSx window; after reset, all address windows on XBUS are
disabled.
BUSCON Switch Control
’0’: Standard switch of bustype (switch of XBCON)
’1’: A bus wait state (Tri-state cycle) is included after execution of last
old-bustype cycle and before the first new-bustype cycle after switch of
XBCON or BUSCON; the BSWC bit is indicated in the old-bustype
XBCON/BUSCON.
’0’: The bus cycle length is controlled by the bus controller using MCTC
’1’: The bus cycle length is controlled by the peripheral using READY
*not used in FC-Cores, where XBCON is hardwired.
RDY
H
ENx
12
rw
/ 8A
WCx
H
BS
11
rw
)
ACTx
BUS
10
rw
CTLx
ALE
rw
9
’x1’: reserved.
ENx
EW
ESFR-b
rw
8
203
7
BTYPx
rw
6
TCx
MT
rw
5
DCx
RW
rw
4
External Bus Interface
Reset Value: 0000
3
2
MCTCx
rw
2001-04-19
1
C161U
0
H