SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 271

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SAF-C161U-LF V1.3

Manufacturer Part Number
SAF-C161U-LF V1.3
Description
IC MCU ISDN 16BIT TTL TQFP-100
Manufacturer
Infineon Technologies
Series
C16xxr
Datasheet

Specifications of SAF-C161U-LF V1.3

Core Processor
C166
Core Size
16-Bit
Speed
36MHz
Connectivity
EBI/EMI, SPI, UART/USART, USB
Peripherals
POR, PWM, WDT
Number Of I /o
56
Program Memory Type
ROMless
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Other names
SAFC161ULFV1.3X
SAFC161ULFV13XP
SP000007502
Figure 80
In wake-up mode received frames are only transferred to the receive buffer register, if
the 9th bit (the wake-up bit) is ‘1’. If this bit is ‘0’, no receive interrupt request will be
activated and no data will be transferred.
This feature may be used to control communication in multi-processor system:
When the master processor wants to transmit a block of data to one of several slaves, it
first sends out an address byte which identifies the target slave. An address byte differs
from a data byte in that the additional 9th bit is a '1' for an address byte and a '0' for a
data byte, so no slave will be interrupted by a data 'byte'. An address 'byte' will interrupt
all slaves (operating in 8-bit data + wake-up bit mode), so each slave can examine the 8
LSBs of the received character (the address). The addressed slave will switch to 9-bit
data mode (eg. by clearing bit CON_M.0), which enables it to also receive the data bytes
that will be coming (having the wake-up bit cleared). The slaves that were not being
addressed remain in 8-bit data + wake-up bit mode, ignoring the following data bytes
IrDA Frames
The modulation schemes of IrDA is based on standard asynchronous data transmission
frames. The asynchronous data format in IrDA mode (CON_M=010
follows :
1 start bit / 8 data bits / 1 stop bit
The coding/decoding of/to the asynchronous data frames is shown in Figure 81. In
general, during the IrDA transmissions UART frames are encoded into IR frames and
vice cersa. A low level on the IR frame indicates a “LED off“ state. A high level on the IR
frame indicates a “LED on“ state.
For a “0“ bit in the UART frame a high pulse is generated. For a “1“ bit in the UART frame
no pulse is generated. The high pulse starts in the middle of a bit cell and has a fixed
Data Sheet
Start
Bit
0
Asynchronous 9-Bit Frames
D0
LSB
D1
D2
11-/12-Bit UART Frame
D3
9 Data Bits
D4
D5 D6
271
CON_M=100
CON_M=101
CON_M=111
Asynchronous/Synchr. Serial Interface
D7
B
B
B
Bit 9
: Bit 9 = Data Bit D8
: Bit 9 = Wake-up Bit
: Bit 9 = Parity Bit
(1st)
Stop
Bit
1
(2nd)
Stop
Bit
1
B
) is defined as
2001-04-19
C161U

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