SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 35

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

For applications which require less than 64 KBytes of address space, a non-segmented
memory model can be selected, where all locations can be addressed by 16 bits, and
thus Port 4 is not needed as an output for the upper address bits (A20/A19/A17...A16),
as is the case when using the segmented memory model.
On-chip XBUS is an internal representation of the external bus and allows to access
integrated application-specific peripherals/modules in the same way as external
components. It provides a defined interface for these customized peripherals.
3.3
The on-chip clock generator provides the C161U with its basic clock signal that controls
all activities of the controller hardware. Its oscillator can either run with an external crystal
and appropriate oscillator circuitry (see also recommendations in chapter „Dedicated
Pins“) or it can be driven by an external oscillator. The oscillator either directly feeds the
external clock signal to the controller hardware (through buffers), divides the external
clock frequency by 2 or 4, or feeds an on-chip phase locked loop (PLL) which multiplies
the input frequency by a selectable factor F. This resulting internal clock signal is also
referred to as “CPU clock”. Two separated clock signals are generated for the CPU itself
and the peripheral part of the chip. While the CPU clock is stopped during the idle mode,
the peripheral clock keeps running. Both clocks are switched off, when the power down
mode is entered.
Note: Pin13 CLKMODE must be connected to LOW signal if an external crystal is used.
The on-chip PLL circuit allows operation of the C161U on a low frequency external clock
while still providing maximum performance. The PLL generates a CPU clock signal with
50% duty cycle. The PLL also provides fail safe mechanisms which allow the detection
of frequency deviations and the execution of emergency actions in case of an external
clock failure.
In addition to the CPU clock, the PLL generates the USB clock which is used for the USB
module only. shows the general clock generation concept of the C161U.
Note: If the USB interface of the C161U is used, an USB clock of 48 MHz is mandatory.
The following constrains must be taken into account when considering the clock concept:
1. The USB clock must be 48 MHz, see the note above. Since there is a fixed PLL
2. If running the USB interface, the CPU clock must be equal or greater than 20 MHz
3. The maximum CPU clock frequency is 36 MHz (18 MIPS).
Data Sheet
prescaler of 1/6, the XTAL1 frequency must be 8 MHz.
Pin cockmode connected to HIGH signal enables the direct input path and
switches the oscillator circuit in power down mode.
In addition, a CPU clock equal or greater than 20 MHz is required in order to
guarantee the full USB functionality. According to Table 8, the only possible input
clock frequency when operating the USB interface is 8 MHz, either using an
external crystal or an direct input clock.
Clock Generation Concept
35
Architectural Overview
2001-04-19
C161U