SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 307

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

SSCCON (FFB2
Data Sheet
EN=0
SSC
Bit
SSCBM
SSCHB
SSCPH
SSCPO
SSCTEN
SSCREN
SSCPEN
SSCBEN
SSCAREN
SSCMS
SSCEN
15
rw
SSC
MS
14
rw
13
-
-
SSC Data Width Selection
SSC Clock Phase Control Bit
SSC Clock Polarity Control Bit
SSC Transmit Error Enable Bit
SSC Receive Error Enable Bit
SSC Phase Error Enable Bit
SSC Baudrate Error Enable Bit
SSC Automatic Reset Enable Bit
SSC Enable Bit = ‘0’
H
Function (Programming Mode, SSCEN = ‘0’)
0 :
1...15 : Transfer Data Width is 2...16 bit (<SSCBM>+1)
SSC Heading Control Bit
0 : Transmit/Receive LSB First
1 : Transmit/Receive MSB First
0 : Shift transmit data on the leading clock edge, latch on trailing edge
1 : Latch receive data on leading clock edge, shift on trailing edge
0 : Idle clock line is low, leading clock edge is low-to-high transition
1 : Idle clock line is high, leading clock edge is high-to-low transition
0 : Ignore transmit errors
1 : Check transmit errors
0 : Ignore receive errors
1 : Check receive errors
0 : Ignore phase errors
1 : Check phase errors
0 : Ignore baudrate errors
1 : Check baudrate errors
0 : No additional action upon a baudrate error
1 : The SSC is automatically reset upon a baudrate error
SSC Master Select Bit
0 : Slave Mode. Operate on shift clock received via SCLK.
1 : Master Mode. Generate shift clock and output it via SCLK.
Transmission and reception disabled. Access to control bits.
AREN
/ D9
SSC
12
rw
H
)
BEN
SSC
Reserved. Do not use this combination.
11
rw
SSC
PEN
10
rw
SSC
REN
rw
9
SSC
TEN
rw
8
SFR
307
High-Speed Synchronous Serial Interface
7
-
-
SSC
PO
rw
6
SSC
PH
rw
5
SSC
HB
rw
4
Reset Value: 0000
3
2
SSCBM
rw
2001-04-19
1
C161U
0
H