SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 191

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

Figure 50
The output of the next address on the external bus can be delayed for a memory or
peripheral, which needs more time to switch off its bus drivers, by introducing a wait state
after the previous bus cycle (see figure above). During this memory tri-state time wait
state, the CPU is not idle, so CPU operations will only be slowed down if a subsequent
external instruction or data fetch operation is required during the next instruction cycle.
The memory tri-state time waitstate requires one CPU clock (28 ns at f
and is controlled via the MTTCx bits of the BUSCON registers. A waitstate will be
inserted, if bit MTTCx is ‘0’ (default after reset).
Note: External bus cycles in multiplexed bus modes implicitly add one tri-state time
Read/Write Signal Delay
C161U allows the user to adjust the timing of the read and write commands to account
for timing requirements of external peripherals. The read/write delay controls the time
between the falling edge of ALE and the falling edge of the command. Without read/write
delay the falling edges of ALE and command(s) are coincident (except for propagation
delays). With the delay enabled, the command(s) become active half a CPU clock after
the falling edge of ALE.
The read/write delay does not extend the memory cycle time, and does not slow down
the controller in general. In multiplexed bus modes, however, the data drivers of an
external device may conflict with the C161U’s address, when the early RD signal is used.
Therefore multiplexed bus cycles should always be programmed with read/write delay.
Data Sheet
Segment
BUS (P0)
ALE
RD
waitstate in addition to the programmable MTTC waitstate.
Memory Tri-State Time
Address
Address
191
Bus Cycle
Data/Instr.
External Bus Interface
MTTC Wait State
CPU
= 36 MHz)
2001-04-19
MCT02065
C161U