SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 281

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SAF-C161U-LF V1.3

Manufacturer Part Number
SAF-C161U-LF V1.3
Description
IC MCU ISDN 16BIT TTL TQFP-100
Manufacturer
Infineon Technologies
Series
C16xxr
Datasheet

Specifications of SAF-C161U-LF V1.3

Core Processor
C166
Core Size
16-Bit
Speed
36MHz
Connectivity
EBI/EMI, SPI, UART/USART, USB
Peripherals
POR, PWM, WDT
Number Of I /o
56
Program Memory Type
ROMless
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Other names
SAFC161ULFV1.3X
SAFC161ULFV13XP
SP000007502
BG represents the contents of the reload register S0BG (BR_VALUE), taken as
unsigned 13-bit integer.
The maximum baudrate that can be achieved for the asynchronous modes when using
the two fixed clock dividers and a module clock of 36 MHz is 1.125 MBaud. Table 59
below lists various commonly used baudrates together with the required reload values
and the deviation errors compared to the intended baudrate.
Table 59
Note: CON_FDE must be 0 to achieve the baudrates in the table above. The deviation
Using the Fractional Divider
When the fractional divider is selected, the input clock f
derived from the module clock f
fractional divider is activated, It divides f
0 to 511. If n=0, the divider ratio is 1 which means that f
divider allows to program the baudrrate with a much better accuracy than with the two
fixed prescaler divider stages.
BG represents the content of the reload register S0BG (BR_VALUE), taken as unsigned
13-bit integer. FDV represents the content of the fractional divider register S0FDV
(FD_VALUE) taken as unsigned 9-bit integer. For example, typical asynchronous
baudrates are shown in Table 61.
Using the fractional divider and a module clock of 36 MHz (equal to the C161U CPU
clock) the available baudrate range is 2.25 MBaud down to 0.5364 Baud.
.
Data Sheet
Baudrate
1.125 MBaud
750.0 kBaud
19.2
9600
4800
2400
1200
errors given in the table above are rounded. Using a baudrate crystal will provide
correct baudrates without deviation errors.
kBaud
Baud
Baud
Baud
Baud
Typical Asynchronous Baudrates using the Fixed Input Clock
Dividers
BRS = ‘0’, f
Deviation
Error
---
---
+ 0.16 %
+ 0.16 %
+ 0.16 %
+ 0.05 %
- 0.69 %
MOD
MOD
= 36 MHz
by a programmable divider. If CON_FDE=1, the
Reload Value Deviation Error Reload
0000
---
003A
0074
00E9
01D3
03A8
MOD
281
H
H
H
H
H
by a fraction of n/512 for any value of n from
H
Asynchronous/Synchr. Serial Interface
DIV
BRS = ‘1’, f
---
---
+ 0.16 %
+ 0.16 %
+ 0.16 %
+ 0.16 %
+/- 0.0 %
=f
DIV
MOD
for the baudrate timer is
. In general, the fractional
MOD
= 36 MHz
Value
---
0000
0026
004D
009B
0137
0270
2001-04-19
H
H
H
H
H
H
C161U

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