SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 364

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

Data Sheet
allows the complete configuration of the controller including its on-chip peripheral units
before releasing the reset signal for the external peripherals of the system.
Watchdog Timer Operation after Reset
The watchdog timer starts running after the internal reset has completed. It will be
clocked with the internal system clock divided by 2 (18 MHz @ f
default reload value is 00
cycles (3.64 ms @ f
disabled, serviced or reprogrammed meanwhile. When the system reset was caused by
a watchdog timer overflow, the WDTR (Watchdog Timer Reset Indication) flag in register
WDTCON will be set to '1'. This indicates the cause of the internal reset to the software
initialization routine. WDTR is reset to '0' by an external hardware reset or by servicing
the watchdog timer. After the internal reset has completed, the operation of the watchdog
timer can be disabled by the DISWDT (Disable Watchdog Timer) instruction. This
instruction has been implemented as a protected instruction. For further security, its
execution is only enabled in the time period after a reset until either the SRVWDT
(Service Watchdog Timer) or the EINIT instruction has been executed. Thereafter the
DISWDT instruction will have no effect.
Note: For a complete description of register WDTCON, refer to Chapter 16.1, page 352.
Reset Values for the C161U Registers
During the reset sequence the registers of the C161U are preset with a default value.
Most SFRs, including system registers and peripheral control and data registers, are
cleared to zero, so all peripherals and the interrupt system are off or idle after reset. A
few exceptions to this rule provide a first pre-initialization, which is either fixed or
controlled by input pins.
DPP1:
DPP2:
DPP3:
CP:
STKUN:
STKOV:
SP:
WDTCON:
S0RBUF:
SSCRB:
SYSCON:
BUSCON0:
RP0H:
ONES:
0001
0002
0003
FC00
FC00
FA00
FC00
00XX
XX
XXXX
0XX0
0XX0
XX
FFFF
H
H
(undefined)
(reset levels of P0H)
H
H
H
H
H
H
H
H
H
H
H
CPU
H
, (value depends on the reset configuration)
(points to data page 1)
(points to data page 2)
(points to data page 3)
(set according to reset configuration)
(set according to reset configuration)
(fixed value)
(undefined)
=36 MHz) after completion of the internal reset, unless it is
H
, so a watchdog timer overflow will occur 131072 CPU clock
364
CPU
=36 MHz), and its
System Reset
2001-04-19
C161U