SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 41

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

C161U
Architectural Overview
Parallel Ports
C161U provides up to 72 I/O lines which are organized into seven input/output ports. All
port lines are bit-addressable, and all input/output lines are individually (bit-wise)
programmable as inputs or outputs via direction registers. The I/O ports are true
bidirectional ports which are switched to high impedance state when configured as
inputs. The output drivers of three I/O ports can be configured (pin by pin) for push/pull
operation or open-drain operation via control registers. During the internal reset, all port
pins are configured as inputs.
All port lines have programmable alternate input or output functions associated with
them. PORT0 and PORT1 may be used as address and data lines when accessing
external memory, while Port 4 outputs the additional segment address bits A20/A19/
A17...A16 in systems where segmentation is used to access more than 64 KBytes of
memory. Port 6 provides optional bus arbitration signals (BREQ, HLDA, HOLD) and chip
select signals. Port 2 accepts the fast external interrupt inputs. Port 3 includes alternate
functions of timers, serial interfaces, the optional bus control signal BHE and the system
clock output (CLKOUT). Port 7 is used for general purpose I/Os. All port lines that are
not used for these alternate functions may be used as general purpose I/O lines.
Serial Channels
Serial communication with other microcontrollers, processors, terminals or external
peripheral components is provided by two serial interfaces with different functionality, an
Asynchronous/Synchronous Serial Channel (ASC) and a High-Speed Synchronous
Serial Channel (SSC).
ASC is upward compatible with the serial ports of the Infineon 8-bit microcontroller
families and supports full-duplex asynchronous communication at up to 2.25 MBaud and
half-duplex synchronous communication at up to 4.5 MBaud @ 36 MHz CPU clock.
A dedicated baud rate generator allows to set up all standard baud rates without
oscillator tuning. For transmission, reception and error handling 4 separate interrupt
vectors are provided. In asynchronous mode, 8- or 9-bit data frames are transmitted or
received, preceded by a start bit and terminated by one or two stop bits. For
multiprocessor communication, a mechanism to distinguish address from data bytes has
been included (8-bit data plus wake up bit mode).
In synchronous mode, the ASC transmits or receives bytes (8 bits) synchronously to a
shift clock which is generated by the ASC. The ASC always shifts the LSB first. A loop
back option is available for testing purposes.
A number of optional hardware error detection capabilities has been included to increase
the reliability of data transfers. A parity bit can automatically be generated on
transmission or be checked on reception. Framing error detection allows to recognize
data frames with missing stop bits. An overrun error will be generated, if the last
character received has not been read out of the receive buffer register at the time the
reception of a new character is complete.
Data Sheet
41
2001-04-19