SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 82

no-image

SAF-C161U-LF V1.3

Manufacturer Part Number
SAF-C161U-LF V1.3
Description
IC MCU ISDN 16BIT TTL TQFP-100
Manufacturer
Infineon Technologies
Series
C16xxr
Datasheet

Specifications of SAF-C161U-LF V1.3

Core Processor
C166
Core Size
16-Bit
Speed
36MHz
Connectivity
EBI/EMI, SPI, UART/USART, USB
Peripherals
POR, PWM, WDT
Number Of I /o
56
Program Memory Type
ROMless
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Other names
SAFC161ULFV1.3X
SAFC161ULFV13XP
SP000007502
Data Sheet
This control mechanism is not triggered, ie. no stack trap is generated, when
• the stack pointer SP is directly updated via MOV instructions
• the limits of the stack area (STKOV, STKUN) are changed, so that SP is outside of the
Multiply/Divide High Register MDH
This register is a part of the 32-bit multiply/divide register, which is implicitly used by the
CPU, when it performs a multiplication or a division. After a multiplication, this non-bit
addressable register represents the high order 16 bits of the 32-bit result. For long
divisions, the MDH register must be loaded with the high order 16 bits of the 32-bit
dividend before the division is started. After any division, register MDH represents the
16-bit remainder.
MDH (FE0C
Whenever this register is updated via software, the Multiply/Divide Register In Use
(MDRIU) flag in the Multiply/Divide Control register (MDC) is set to '1'.
When a multiplication or division is interrupted before its completion and when a new
multiply or divide operation is to be performed within the interrupt service routine, register
MDH must be saved along with registers MDL and MDC to avoid erroneous results.
A detailed description of how to use the MDH register for programming multiply and
divide algorithms can be found in chapter “System Programming”.
Multiply/Divide Low Register MDL
This register is a part of the 32-bit multiply/divide register, which is implicitly used by the
CPU, when it performs a multiplication or a division. After a multiplication, this non-bit
addressable register represents the low order 16 bits of the 32-bit result. For long
divisions, the MDL register must be loaded with the low order 16 bits of the 32-bit
dividend before the division is started. After any division, register MDL represents the 16-
bit quotient.
Bit
mdh
15
new limits.
14
H
13
/ 06
Function
Specifies the high order 16 bits of the 32-bit multiply and divide register
MD.
H
)
12
11
10
9
8
SFR
mdh
rw
82
7
6
5
4
Central Processor Unit
Reset Value: 0000
3
2
2001-04-19
1
C161U
0
H

Related parts for SAF-C161U-LF V1.3